Inventor

SHUM CHUNG-LUNG K

US296 patents

⚠️ This page may combine multiple inventors who share the name “SHUM CHUNG-LUNG K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHUM CHUNG-LUNG K

IBM

Fingerprint-initiated trace extraction

Controlling operation of a run-time instrumentation facility from a lesser-privileged state

Hybrid tracking of transaction read and write sets

Instruction to cancel outstanding cache prefetches

Flushing speculative instruction processing

Using the transaction-begin instruction to manage transactional aborts in transactional memory computing environments

Using the transaction-begin instruction to manage transactional aborts in transactional memory computing environments

Coalescing memory transactions

Disowning cache entries on aging out of the entry

Reducing cache transfer overhead in a system

Hint instruction for managing transactional aborts in transactional memory computing environments

Hardware transaction transient conflict resolution

Latent modification instruction for transactional execution

Transactional memory operations with write-only atomicity

Transactional memory operations with read-only atomicity

Dynamic prediction of hardware transaction resource requirements

Predicting the length of a transaction

Hybrid tracking of transaction read and write sets

Multi-granular cache management in multi-processor computing environments

Dynamic releasing of cache lines

Code optimization to enable and disable coalescing of memory transactions

Hybrid tracking of transaction read and write sets

Speculation control for improving transaction success rate, and instruction therefor

Latent modification instruction for transactional execution

Software enabled and disabled coalescing of memory transactions

Configurable code fingerprint

Automated compiler operation verification

Multithreaded transactions

Multithreaded transactions

Transactional memory operations with write-only atomicity

Dynamic prediction of concurrent hardware transactions resource requirements and allocation

Salvaging lock elision transactions with instructions to change execution type

Salvaging lock elision transactions with instructions to change execution type

Coalescing memory transactions

Programmable code fingerprint

Software indications and hints for coalescing memory transactions

Code optimization to enable and disable coalescing of memory transactions

Operand fetching control as a function of branch confidence

Variable acknowledge rate to reduce bus contention in presence of communication errors

Centralized management of high-contention cache lines in multi-processor computing environments

Parallel cache interleave accesses with address-sliced directories

BUSABA FADI Y

Hardware recovery in multi-threaded processor

Reconfigurable recovery modes in high availability processors

Management of migrating threads within a computing environment to transform multiple threading mode processors to single thread mode processors

Variable acknowledge rate to reduce bus contention in presence of communication errors

FARRELL MARK S

Determining the status of run-time-instrumentation controls

Modifying run-time-instrumentation controls from a lesser-privileged state

GLOBALFOUNDRIES INC

Managing high-conflict cache lines in transactional memory computing environments

ALEXANDER KHARY J

Early instruction text based operand store compare reject avoidance

GREINER DAN F

Non-quiescing key setting facility