Inventor

ROY KAUSHIK

US51 patents

⚠️ This page may combine multiple inventors who share the name “ROY KAUSHIK”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ROY KAUSHIK

PURDUE RESEARCH FOUNDATION

System and method for in-memory computing

Multi-bit dot product engine

Memory cell with built-in process variation tolerance

Electronic comparison systems

Self-repairing technique in nano-scale SRAM to reduce parametric failures

Sense amplifier circuit

Static random access memory cell and devices using same

Method and circuit for reducing leakage and increasing read stability in a memory device

Electronic comparison systems

Memory device having in-situ in-memory stateful vector logic operation

Electronic comparison systems

Electronic memory including ROM and RAM

Buffered spin-torque sensing device for global interconnect circuits

Electronic synapse having spin-orbit torque induced spike-timing dependent plasticity

Vehicle battery current sensing system

Vehicle battery current sensing system

Synthesis approach for active leakage power reduction using dynamic supply gating

In-memory bit-serial addition system

In-memory bit-serial addition system

Approximate cache memory

Approximate cache memory

Apparatus and methods for determining memory device faults

Sparsity-aware reconfigurable compute-in-memory (CIM) static random access memory (SRAM)

Spin orbit torque based electronic neuron

Intelligent non-intrusive load monitoring system

High accuracy non-invasive current sensor system

KHAN MOHAMMAD

Display screen with graphical user interface

Display screen with graphical user interface

Display screen with graphical user interface

Methods, systems, and computer readable media for detecting customer presence to initiate the ordering and purchase of goods and services

Methods, systems, and computer readable media for secure near field communication of a non-secure memory element payload

TEXAS INSTRUMENTS INC

Method of segmenting an FPGA channel architecture for maximum routability and performance

Circuit activity driven state assignment of FSMS implemented in CMOS for low power reliable operations

Circuit activity driven multilevel logic optimization for low power reliable operation

SEQUENT SOFTWARE INC

System and method for initially establishing and periodically confirming trust in a software application

System and method for initially establishing and periodically confirming trust in a software application

System and method for initially establishing and periodically confirming trust in a software application

MASTERCARD INTERNATIONAL INC

Methods, systems, and computer readable media for detecting customer presence to initiate the ordering and purchase of goods and services

Methods, systems, and computer readable media for detecting customer presence to initiate the ordering and purchase of goods and services

Methods, systems, and computer readable media for secure near field communication of a non-secure memory element payload

IBM

Sense-amp based adder with source follower pass gate evaluation tree

Sense-amp based adder with source follower evaluation tree

VIVOTECH INC

Graphical user interface for a display screen or portion thereof

INTEL CORP

Differential current switch logic gate

ROY KAUSHIK

Efficient power conversion for ultra low voltage micro scale energy transducers

ORACLE INT CORP

Declarative task-based user interfaces

SAMSUNG ELECTRONICS CO LTD

System and method for mobile wallet remittance

GOOGLE LLC

Selective text prediction for electronic messaging

YASEEN RAHIM MOHAMED

Declarative task-based user interfaces

PURDUE RES FOUNDATION PURDUE U

Low power scan design and delay fault testing technique using first level supply gating