Inventor

SLEGEL TIMOTHY J

US365 patents

⚠️ This page may combine multiple inventors who share the name “SLEGEL TIMOTHY J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SLEGEL TIMOTHY J

IBM

Method, system and program product for invalidating a range of selected storage translation table entries

Invalidating storage, clearing buffer entries, and an instruction therefor

Blocking processing restrictions based on addresses

Program event recording within a transactional environment

Intra-instructional transaction abort handling

Controlling operation of a run-time instrumentation facility from a lesser-privileged state

Restricted instructions in transactional execution

Restricted instructions in transactional execution

Conditional transaction end instruction

Prefetching of discontiguous storage locations in anticipation of transactional execution

Using the transaction-begin instruction to manage transactional aborts in transactional memory computing environments

Using the transaction-begin instruction to manage transactional aborts in transactional memory computing environments

Emulating execution of a perform frame management instruction

Transactional execution branch indications

Load page table entry address instruction execution based on an address translation format control field

Method, system and computer program product for failure analysis implementing automated comparison of multiple reference models

Error accumulation register, error accumulation method, and error accumulation system

Cipher message with authentication instruction

Rotate then operate on selected bits facility and instructions therefore

Filtering processor requests based on identifiers

System and method for providing processor recovery in a multi-core system

Blocking processing restrictions based on page indices

Method and apparatus for error recovery in arrays

Nontransactional store instruction

Conditional transaction end instruction

Facilitating transaction completion subsequent to repeated aborts of the transaction

Prioritization of transactions based on execution by transactional core with super core indicator

Test pending external interruption instruction

Conditional instruction end operation

Hint instruction for managing transactional aborts in transactional memory computing environments

Randomized testing within transactional execution

Transaction begin/end instructions

Hardware transaction transient conflict resolution

Latent modification instruction for transactional execution

Conditional transaction end instruction

Transaction abort instruction specifying a reason for abort

Facilitating transaction completion subsequent to repeated aborts of the transaction

GREINER DAN F

Program event recording within a transactional environment

Saving/restoring selected registers in transactional processing

Transaction diagnostic block

Transactional processing

Constrained transaction execution

Perform frame management function instruction for setting storage keys and clearing blocks of main storage

Dynamic address translation with frame management

Extract cache attribute facility and instruction therefore

Dynamic address translation with change record override

Dynamic address translation with translation table entry format control for indentifying format of the translation table entry

JACOBI CHRISTIAN

Load pair disjoint facility and instruction therefore

SLEGEL TIMOTHY J

Invalidating a range of two or more translation table entries and instruction therefore

HELLER LISA C

System, method and computer program product for providing a programmable quiesce filtering register