Inventor
MACPHERSON MIKE
US44 patents
Patents
44 patentsUS11620256B2Apr 4, 2023
Systems and methods for improving cache efficiency and utilization
INTEL CORP36 citations97
US11113784B2Sep 7, 2021
Sparse optimizations for a matrix accelerator architecture
INTEL CORP46 citations97
US12079155B2Sep 3, 2024
Graphics processor operation scheduling for deterministic latency
INTEL CORP6 citations93
US12204487B2Jan 21, 2025
Graphics processor data access and sharing
INTEL CORP2 citations86
US11842423B2Dec 12, 2023
Dot product operations on sparse matrix elements
INTEL CORP4 citations86
US11410024B2Aug 9, 2022
Tool for facilitating efficiency in machine learning
INTEL CORP7 citations86
US12210477B2Jan 28, 2025
Systems and methods for improving cache efficiency and utilization
INTEL CORP2 citations85
US11676239B2Jun 13, 2023
Sparse optimizations for a matrix accelerator architecture
INTEL CORP10 citations85
US12182062B1Dec 31, 2024
Multi-tile memory management
INTEL CORP2 citations84
US12141094B2Nov 12, 2024
Systolic disaggregation within a matrix accelerator architecture
INTEL CORP2 citations84
US11995029B2May 28, 2024
Multi-tile memory management for detecting cross tile access providing multi-tile inference scaling and providing page migration
INTEL CORP2 citations84
US11899614B2Feb 13, 2024
Instruction based control of memory attributes
INTEL CORP2 citations84
US10909039B2Feb 2, 2021
Data prefetching for graphics data processing
INTEL CORP5 citations84
US11016929B2May 25, 2021
Scalar core integration
INTEL CORP7 citations83
US12066975B2Aug 20, 2024
Cache structure and utilization
INTEL CORP2 citations82
US11934342B2Mar 19, 2024
Assistance for hardware prefetch in cache access
INTEL CORP3 citations74
US12561277B2Feb 24, 2026
Memory controller management techniques for managing data transfer for memory access operations
INTEL CORP0 citations73
US12561276B2Feb 24, 2026
Systems and methods for updating memory side caches in a multi-GPU configuration
INTEL CORP0 citations73
US12321310B2Jun 3, 2025
Implicit fence for write messages
INTEL CORP0 citations73
US12242414B2Mar 4, 2025
Data initialization techniques
INTEL CORP0 citations73
US12153541B2Nov 26, 2024
Cache structure and utilization
INTEL CORP0 citations73
US12099461B2Sep 24, 2024
Multi-tile memory management
INTEL CORP0 citations73
US11762804B2Sep 19, 2023
Scalar core integration
INTEL CORP1 citations73
US11409693B2Aug 9, 2022
Scalar core integration
INTEL CORP2 citations73
US11232533B2Jan 25, 2022
Memory prefetching in multiple GPU environment
INTEL CORP4 citations73
US11119820B2Sep 14, 2021
Local memory sharing between kernels
INTEL CORP3 citations73
US12554674B2Feb 17, 2026
Multi-tile memory management
INTEL CORP0 citations72
US12093210B2Sep 17, 2024
Compression techniques
INTEL CORP1 citations72
US11151769B2Oct 19, 2021
Graphics architecture including a neural network pipeline
INTEL CORP2 citations71
US12373912B2Jul 29, 2025
Prefetch status notification for memory prefetching
INTEL CORP0 citations63
US12346694B2Jul 1, 2025
Register file for systolic array
INTEL CORP1 citations63
US11861759B2Jan 2, 2024
Memory prefetching in multiple GPU environment
INTEL CORP0 citations63
US11809905B2Nov 7, 2023
Local memory sharing between kernels
INTEL CORP0 citations63
US12293431B2May 6, 2025
Sparse optimizations for a matrix accelerator architecture
INTEL CORP0 citations62
US12198222B2Jan 14, 2025
Architecture for block sparse operations on a systolic array
INTEL CORP0 citations62
US12117962B2Oct 15, 2024
Scalar core integration
INTEL CORP0 citations62
US12001944B2Jun 4, 2024
Tool for facilitating efficiency in machine learning
INTEL CORP1 citations62
US11892950B2Feb 6, 2024
Data prefetching for graphics data processing
INTEL CORP0 citations62
US11409658B2Aug 9, 2022
Data prefetching for graphics data processing
INTEL CORP0 citations62
US12229867B2Feb 18, 2025
Graphics architecture including a neural network pipeline
INTEL CORP0 citations61
US11676322B2Jun 13, 2023
Graphics architecture including a neural network pipeline
INTEL CORP0 citations61
US12254526B2Mar 18, 2025
On chip dense memory for temporal buffering
INTEL CORP0 citations52
US7603673B2Oct 13, 2009
Method and system for reducing context switch times
INTEL CORP0 citations52
US12399685B2Aug 26, 2025
Systolic array having support for output sparsity
INTEL CORP0 citations50