Inventor
ANANTARAMAN ARAVINDH
US50 patents
Patents
50 patentsUS11620256B2Apr 4, 2023
Systems and methods for improving cache efficiency and utilization
INTEL CORP36 citations97
US12204487B2Jan 21, 2025
Graphics processor data access and sharing
INTEL CORP2 citations86
US12182035B2Dec 31, 2024
Systems and methods for cache optimization
INTEL CORP6 citations86
US12210477B2Jan 28, 2025
Systems and methods for improving cache efficiency and utilization
INTEL CORP2 citations85
US12013808B2Jun 18, 2024
Multi-tile architecture for graphics operations
INTEL CORP3 citations85
US12182062B1Dec 31, 2024
Multi-tile memory management
INTEL CORP2 citations84
US11995029B2May 28, 2024
Multi-tile memory management for detecting cross tile access providing multi-tile inference scaling and providing page migration
INTEL CORP2 citations84
US11899614B2Feb 13, 2024
Instruction based control of memory attributes
INTEL CORP2 citations84
US10909039B2Feb 2, 2021
Data prefetching for graphics data processing
INTEL CORP5 citations84
US11016929B2May 25, 2021
Scalar core integration
INTEL CORP7 citations83
US12066975B2Aug 20, 2024
Cache structure and utilization
INTEL CORP2 citations82
US12124383B2Oct 22, 2024
Systems and methods for cache optimization
INTEL CORP3 citations75
US12056059B2Aug 6, 2024
Systems and methods for cache optimization
INTEL CORP3 citations75
US11934342B2Mar 19, 2024
Assistance for hardware prefetch in cache access
INTEL CORP3 citations74
US12561276B2Feb 24, 2026
Systems and methods for updating memory side caches in a multi-GPU configuration
INTEL CORP0 citations73
US12561277B2Feb 24, 2026
Memory controller management techniques for managing data transfer for memory access operations
INTEL CORP0 citations73
US12321310B2Jun 3, 2025
Implicit fence for write messages
INTEL CORP0 citations73
US12242414B2Mar 4, 2025
Data initialization techniques
INTEL CORP0 citations73
US12153541B2Nov 26, 2024
Cache structure and utilization
INTEL CORP0 citations73
US12099461B2Sep 24, 2024
Multi-tile memory management
INTEL CORP0 citations73
US11762804B2Sep 19, 2023
Scalar core integration
INTEL CORP1 citations73
US11409693B2Aug 9, 2022
Scalar core integration
INTEL CORP2 citations73
US11232533B2Jan 25, 2022
Memory prefetching in multiple GPU environment
INTEL CORP4 citations73
US11227358B2Jan 18, 2022
Systems and methods for exploiting queues and transitional storage for improved low-latency high-bandwidth on-die data retrieval
INTEL CORP2 citations73
US11157431B2Oct 26, 2021
System, apparatus and method for multi-die distributed memory mapped input/output support
INTEL CORP3 citations73
US11119820B2Sep 14, 2021
Local memory sharing between kernels
INTEL CORP3 citations73
US12554674B2Feb 17, 2026
Multi-tile memory management
INTEL CORP0 citations72
US12093210B2Sep 17, 2024
Compression techniques
INTEL CORP1 citations72
US10204047B2Feb 12, 2019
Memory controller for multi-level system memory with coherency unit
INTEL CORP2 citations70
US11386013B2Jul 12, 2022
Dynamic cache control mechanism
INTEL CORP3 citations66
US12130739B2Oct 29, 2024
Apparatuses, methods, and systems for dynamic bypassing of last level cache
INTEL CORP2 citations64
US12373912B2Jul 29, 2025
Prefetch status notification for memory prefetching
INTEL CORP0 citations63
US11861759B2Jan 2, 2024
Memory prefetching in multiple GPU environment
INTEL CORP0 citations63
US11809905B2Nov 7, 2023
Local memory sharing between kernels
INTEL CORP0 citations63
US11561828B2Jan 24, 2023
Graphics systems and methods for accelerating synchronization using fine grain dependency check and scheduling optimizations based on available shared memory space
INTEL CORP0 citations63
US11036545B2Jun 15, 2021
Graphics systems and methods for accelerating synchronization using fine grain dependency check and scheduling optimizations based on available shared memory space
INTEL CORP1 citations63
US12223353B2Feb 11, 2025
Systems and methods for synchronization of multi-thread lanes
INTEL CORP0 citations62
US12117962B2Oct 15, 2024
Scalar core integration
INTEL CORP0 citations62
US11892950B2Feb 6, 2024
Data prefetching for graphics data processing
INTEL CORP0 citations62
US11869113B2Jan 9, 2024
Systems and methods for exploiting queues and transitional storage for improved low-latency high-bandwidth on-die data retrieval
INTEL CORP0 citations62
US11816500B2Nov 14, 2023
Systems and methods for synchronization of multi-thread lanes
INTEL CORP0 citations62
US11409658B2Aug 9, 2022
Data prefetching for graphics data processing
INTEL CORP0 citations62
US12572392B2Mar 10, 2026
Flexible partitioning of GPU resources
INTEL CORP0 citations61
US12499503B2Dec 16, 2025
Multi-render partitioning
INTEL CORP0 citations61
US11416411B2Aug 16, 2022
Preemptive page fault handling
INTEL CORP1 citations61
US11249910B2Feb 15, 2022
Initialization and management of class of service attributes in runtime to optimize deep learning training in distributed environments
INTEL CORP0 citations59
US11231927B2Jan 25, 2022
System, apparatus and method for providing a fabric for an accelerator
INTEL CORP1 citations58
US12254526B2Mar 18, 2025
On chip dense memory for temporal buffering
INTEL CORP0 citations52
US11321262B2May 3, 2022
Interconnected systems fence mechanism
INTEL CORP0 citations52
US12373348B2Jul 29, 2025
Atomic handling for disaggregated 3D structured SoCs
INTEL CORP0 citations47