Inventor

GOPALAKRISHNAN LIJI

US46 patents

⚠️ This page may combine multiple inventors who share the name “GOPALAKRISHNAN LIJI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GOPALAKRISHNAN LIJI

RAMBUS INC

Memory with alternative command interfaces

Memory component with command-triggered data clock distribution

Energy-efficient error-correction-detection storage

Memory component with staggered power-down exit

Communication via a memory interface

Energy-efficient error-correction-detection storage

Calibration protocol for command and address bus voltage reference in low-swing single-ended signaling

Multi-cycle write leveling

Memory controller with reconfigurable hardware

Load-reduced DRAM stack

Memory system with multiple open rows per bank

Memory with alternative command interfaces

Memory with alternative command interfaces

Calibration protocol for command and address bus voltage reference in low-swing single-ended signaling

Memory device with multi-mode deserializer

Load-reduced DRAM stack

Partial array refresh timing

Memory system with multiple open rows per bank

Command-triggered data clock distribution mode

Command-triggered data clock distribution mode

Partial array refresh timing

Memory module with configurable command buffer

Command-triggered data clock distribution

Securing address information in a memory controller

Memory with alternative command interfaces

Memory system with multiple open rows per bank

Energy-efficient error-correction-detection storage

Energy-efficient error-correction-detection storage

Dedicated cache-related block transfer in a memory system

DRAM interface mode with interruptible internal transfer operation

Energy-efficient error-correction-detection storage

Dedicated cache-related block transfer in a memory system

Dedicated cache-related block transfer in a memory system

DRAM interface mode with interruptible internal transfer operation

Flash memory device having a calibration mode

Flash memory device having a calibration mode

Calibration protocol for command and address bus voltage reference in low-swing single-ended signaling

Hierarchical bank group timing

Memory component with independently enabled data and command interfaces

Memory with alternative command interfaces

Communication via a memory interface

Staggered exit from memory power-down

Power-management for integrated circuits

Calibration protocol for command and address bus voltage reference in low-swing single-ended signaling

Calibration protocol for command and address bus voltage reference in low-swing single-ended signaling

SHAEFFER IAN

Power-management for integrated circuits