Inventor
RAMALINGAM ANAND S
US32 patents
⚠️ This page may combine multiple inventors who share the name “RAMALINGAM ANAND S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
22 patentsUS9851905B1Dec 26, 2017
Concurrent memory operations for read operation preemption
INTEL CORP25 citations94
US10126958B2Nov 13, 2018
Write suppression in non-volatile memory
INTEL CORP8 citations84
US10008250B2Jun 26, 2018
Single level cell write buffering for multiple level cell non-volatile memory
INTEL CORP10 citations84
US9811269B1Nov 7, 2017
Achieving consistent read times in multi-level non-volatile memory
INTEL CORP6 citations84
US9760281B2Sep 12, 2017
Sequential write stream management
INTEL CORP10 citations84
US9870169B2Jan 16, 2018
Interleaved all-level programming of non-volatile memory
INTEL CORP10 citations83
US10528462B2Jan 7, 2020
Storage device having improved write uniformity stability
INTEL CORP3 citations73
US10275156B2Apr 30, 2019
Managing solid state drive defect redundancies at sub-block granularity
INTEL CORP2 citations73
US10254977B2Apr 9, 2019
Achieving consistent read times in multi-level non-volatile memory
INTEL CORP4 citations73
US10133668B2Nov 20, 2018
Technologies for providing cross data storage device communications
INTEL CORP3 citations73
US10120751B2Nov 6, 2018
Techniques to recover data using exclusive OR (XOR) parity information
INTEL CORP4 citations73
US9778848B2Oct 3, 2017
Method and apparatus for improving read performance of a solid state drive
INTEL CORP3 citations73
US10866737B2Dec 15, 2020
Apparatus, method and system to store information for a solid state drive
INTEL CORP2 citations72
US10528463B2Jan 7, 2020
Technologies for combining logical-to-physical address table updates in a single write operation
INTEL CORP3 citations72
US10146440B2Dec 4, 2018
Apparatus, system and method for offloading collision check operations in a storage device
INTEL CORP4 citations71
US11210130B2Dec 28, 2021
Adaptive write acknowledgment for storage devices
INTEL CORP0 citations56
US10871903B2Dec 22, 2020
Achieving consistent read times in multi-level non-volatile memory
INTEL CORP0 citations52
US10210032B2Feb 19, 2019
Processing commands via dedicated register pairs for each thread of a plurality of threads
INTEL CORP0 citations52
US10114556B2Oct 30, 2018
Method and apparatus for improving read performance of a solid state drive
INTEL CORP0 citations52
US9870462B2Jan 16, 2018
Prevention of cable-swap security attack on storage devices
INTEL CORP1 citations52
US7468996B2Dec 23, 2008
External cavity laser tuning element dither servo control
INTEL CORP0 citations51
US10203888B2Feb 12, 2019
Technologies for performing a data copy operation on a data storage device with a power-fail-safe data structure
INTEL CORP0 citations42
MICRON TECHNOLOGY INC
4 patentsUS9477616B2Oct 25, 2016
Devices, systems, and methods of reducing chip select
MICRON TECHNOLOGY INC4 citations83
US10289597B2May 14, 2019
Devices, systems, and methods of reducing chip select
MICRON TECHNOLOGY INC1 citations72
US9996496B2Jun 12, 2018
Devices, systems, and methods of reducing chip select
MICRON TECHNOLOGY INC2 citations72
US9785603B2Oct 10, 2017
Devices, systems, and methods of reducing chip select
MICRON TECHNOLOGY INC2 citations72
SK HYNIX NAND PRODUCT SOLUTIONS CORP
4 patentsUS12561090B2Feb 24, 2026
NAND-based storage device with partitioned nonvolatile write buffer
SK HYNIX NAND PRODUCT SOLUTIONS CORP0 citations60
US12197776B2Jan 14, 2025
NAND-based storage device with partitioned nonvolatile write buffer
SK HYNIX NAND PRODUCT SOLUTIONS CORP0 citations60
US11709623B2Jul 25, 2023
NAND-based storage device with partitioned nonvolatile write buffer
SK HYNIX NAND PRODUCT SOLUTIONS CORP0 citations60
US12340113B2Jun 24, 2025
Host controlled garbage collection in a solid state drive
SK HYNIX NAND PRODUCT SOLUTIONS CORP0 citations46