Inventor
TRIKA SANJEEV N
US86 patents
⚠️ This page may combine multiple inventors who share the name “TRIKA SANJEEV N”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
42 patentsUS7516267B2Apr 7, 2009
Recovering from a non-volatile memory failure
INTEL CORP146 citations99
US7941692B2May 10, 2011
NAND power fail recovery
INTEL CORP116 citations97
US9671971B2Jun 6, 2017
Managing prior versions of data for logical addresses in a storage device
INTEL CORP36 citations93
US6630931B1Oct 7, 2003
Generation of stereoscopic displays using image approximation
INTEL CORP38 citations93
US6366282B1Apr 2, 2002
Method and apparatus for morphing objects by subdividing and mapping portions of the objects
INTEL CORP35 citations93
US6362833B2Mar 26, 2002
Method and apparatus for progressively constructing a series of morphs between two-dimensional or three-dimensional models
INTEL CORP25 citations93
US7797479B2Sep 14, 2010
Technique to write to a non-volatile memory
INTEL CORP27 citations92
US7231497B2Jun 12, 2007
Merging write-back and write-through cache policies
INTEL CORP40 citations92
US7138998B2Nov 21, 2006
Multi-resolution spatial partitioning
INTEL CORP26 citations89
US11687498B2Jun 27, 2023
Storage appliance for processing of functions as a service (FaaS)
INTEL CORP5 citations86
US10078453B1Sep 18, 2018
Storage system, computer program product, and method for managing a hybrid memory device system
INTEL CORP17 citations86
US10831734B2Nov 10, 2020
Update-insert for key-value storage interface
INTEL CORP7 citations84
US10430333B2Oct 1, 2019
Storage system with interconnected solid state disks
INTEL CORP8 citations84
US7640395B2Dec 29, 2009
Maintaining write ordering in a system
INTEL CORP15 citations84
US6219058B1Apr 17, 2001
Bin-per-span based representation and communication of graphical data
INTEL CORP18 citations84
US9910786B2Mar 6, 2018
Efficient redundant array of independent disks (RAID) write hole solutions
INTEL CORP13 citations83
US7966456B2Jun 21, 2011
Method for reducing number of writes in a cache memory
INTEL CORP14 citations79
US11042323B2Jun 22, 2021
Offload defrag operation for host-managed storage
INTEL CORP2 citations73
US11010350B2May 18, 2021
Storage appliance for processing of functions as a service (FaaS)
INTEL CORP3 citations73
US10970207B2Apr 6, 2021
Storage system with interconnected solid state disks
INTEL CORP1 citations73
US10915267B2Feb 9, 2021
Atomic cross-media writes on a storage device
INTEL CORP3 citations73
US10761779B2Sep 1, 2020
Storage compute offloads on sharded and erasure-coded data
INTEL CORP4 citations73
US10700703B2Jun 30, 2020
Dynamic reliability levels for storage devices
INTEL CORP3 citations73
US10620870B2Apr 14, 2020
Data storage device with bytewise copy
INTEL CORP6 citations73
US10416900B2Sep 17, 2019
Technologies for addressing data in a memory
INTEL CORP2 citations73
US10409500B2Sep 10, 2019
Multiple indirection granularities for mass storage devices
INTEL CORP2 citations73
US10365844B2Jul 30, 2019
Logical block address to physical block address (L2P) table compression
INTEL CORP2 citations73
US7962785B2Jun 14, 2011
Method and apparatus to maintain data integrity in disk cache memory during and after periods of cache inaccessibility
INTEL CORP5 citations73
US7627713B2Dec 1, 2009
Method and apparatus to maintain data integrity in disk cache memory during and after periods of cache inaccessibility
INTEL CORP5 citations73
US10528463B2Jan 7, 2020
Technologies for combining logical-to-physical address table updates in a single write operation
INTEL CORP3 citations72
US10482010B2Nov 19, 2019
Persistent host memory buffer
INTEL CORP2 citations72
US10466917B2Nov 5, 2019
Indirection structure prefetch based on prior state information
INTEL CORP3 citations72
US10296224B2May 21, 2019
Apparatus, system and method for increasing the capacity of a storage device available to store user data
INTEL CORP2 citations72
US12112055B2Oct 8, 2024
Erasure coding write hole closure for solid-state drive (SSD) erasure coding
INTEL CORP2 citations71
US10747439B2Aug 18, 2020
Method and apparatus for power-fail safe compression and dynamic capacity for a storage device
INTEL CORP2 citations71
US10417218B2Sep 17, 2019
Techniques to achieve ordering among storage device transactions
INTEL CORP2 citations71
US10146440B2Dec 4, 2018
Apparatus, system and method for offloading collision check operations in a storage device
INTEL CORP4 citations71
US9471448B2Oct 18, 2016
Performing an atomic write operation across multiple storage devices
INTEL CORP5 citations71
US10216415B2Feb 26, 2019
Computer program product, system, and method for dynamically increasing the capacity of a storage device
INTEL CORP2 citations70
US9652384B2May 16, 2017
Apparatus, system and method for caching compressed data
INTEL CORP5 citations70
US9047172B2Jun 2, 2015
Adaptive power control of memory map storage devices
INTEL CORP4 citations69
US9921914B2Mar 20, 2018
Redundant array of independent disks (RAID) write hole solutions
INTEL CORP3 citations68
TRIKA SANJEEV N
3 patentsUS8195891B2Jun 5, 2012
Techniques to perform power fail-safe caching without atomic metadata
TRIKA SANJEEV N26 citations92
US8171219B2May 1, 2012
Method and system to perform caching based on file-level heuristics
TRIKA SANJEEV N12 citations80
US9448922B2Sep 20, 2016
High-performance storage structures and systems featuring multiple non-volatile memories
TRIKA SANJEEV N6 citations73
RATN PRASUN
2 patentsROYER ROBERT
2 patentsMANGOLD RICHARD P
1 patentShowing the top 50 of 86 patents by PatentIndex Score.