Inventor
HILL DAVID L
US39 patents
⚠️ This page may combine multiple inventors who share the name “HILL DAVID L”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
26 patentsUS6601121B2Jul 29, 2003
Quad pumped bus architecture and protocol
INTEL CORP104 citations99
US6499090B1Dec 24, 2002
Prioritized bus request scheduling mechanism for processing devices
INTEL CORP80 citations99
US7363474B2Apr 22, 2008
Method and apparatus for suspending execution of a thread until a specified memory access occurs
INTEL CORP104 citations97
US7127561B2Oct 24, 2006
Coherency techniques for suspending execution of a thread until a specified memory access occurs
INTEL CORP95 citations97
US7487305B2Feb 3, 2009
Prioritized bus request scheduling mechanism for processing devices
INTEL CORP50 citations96
US6782457B2Aug 24, 2004
Prioritized bus request scheduling mechanism for processing devices
INTEL CORP33 citations96
US6609171B1Aug 19, 2003
Quad pumped bus architecture and protocol
INTEL CORP34 citations96
US6606692B2Aug 12, 2003
Prioritized bus request scheduling mechanism for processing devices
INTEL CORP29 citations96
US6732242B2May 4, 2004
External bus transaction scheduling system
INTEL CORP63 citations95
US6484239B1Nov 19, 2002
Prefetch queue
INTEL CORP49 citations94
US6907487B2Jun 14, 2005
Enhanced highly pipelined bus architecture
INTEL CORP22 citations93
US6880031B2Apr 12, 2005
Snoop phase in a highly pipelined bus architecture
INTEL CORP18 citations93
US6807592B2Oct 19, 2004
Quad pumped bus architecture and protocol
INTEL CORP16 citations93
US6804735B2Oct 12, 2004
Response and data phases in a highly pipelined bus architecture
INTEL CORP21 citations93
US6216208B1Apr 10, 2001
Prefetch queue responsive to read request sequences
INTEL CORP39 citations92
US6078981AJun 20, 2000
Transaction stall technique to prevent livelock in multiple-processor systems
INTEL CORP33 citations92
US6557081B2Apr 29, 2003
Prefetch queue
INTEL CORP16 citations91
US7133981B2Nov 7, 2006
Prioritized bus request scheduling mechanism for processing devices
INTEL CORP8 citations74
US7143242B2Nov 28, 2006
Dynamic priority external transaction system
INTEL CORP8 citations73
US6654837B1Nov 25, 2003
Dynamic priority external transaction system
INTEL CORP10 citations73
US6401172B1Jun 4, 2002
Recycle mechanism for a processing agent
INTEL CORP6 citations73
US6209068B1Mar 27, 2001
Read line buffer and signaling protocol for processor
INTEL CORP12 citations73
US6742085B2May 25, 2004
Prefetch queue
INTEL CORP9 citations67
US7783809B2Aug 24, 2010
Virtualization of pin functionality in a point-to-point interface
INTEL CORP2 citations62
US6412091B2Jun 25, 2002
Error correction system in a processing agent having minimal delay
INTEL CORP3 citations62
US6269465B1Jul 31, 2001
Error correction system in a processing agent having minimal delay
INTEL CORP2 citations62
NEWMONT GOLD CO
3 patentsUS5246486ASep 21, 1993
Biooxidation process for recovery of gold from heaps of low-grade sulfidic and carbonaceous sulfidic ore materials
NEWMONT GOLD CO123 citations97
US5332559AJul 26, 1994
Biooxidation process for recovery of metal values from sulphur-containing ore materials
NEWMONT GOLD CO108 citations96
US5834294ANov 10, 1998
Biooxidation process for recovery of metal values from sulfur-containing ore materials
NEWMONT GOLD CO34 citations92