Inventor

LEE KYOUNG-WOO

KR61 patents

⚠️ This page may combine multiple inventors who share the name “LEE KYOUNG-WOO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEE KYOUNG-WOO

SAMSUNG ELECTRONICS CO LTD

Structure of a CMOS image sensor and method for fabricating the same

Method for storing parity and rebuilding data contents of failed disks in an external storage subsystem and apparatus thereof

Method for forming dual damascene structure in semiconductor device

Methods for forming self-aligned dual stress liners for CMOS semiconductor devices

Methods of forming CMOS integrated circuit devices having stressed NMOS and PMOS channel regions therein and circuits formed thereby

Structure of a CMOS image sensor and method for fabricating the same

Method of fabricating dual damascene interconnections of microelectronic device using hybrid low k-dielectric and carbon-free inorganic filler

Method for forming metal wiring layer of semiconductor device

Method of manufacturing interconnection line in semiconductor device

Semiconductor device having crack stop structure

Method of fabricating dual damascene interconnection and etchant for stripping sacrificial layer

Semiconductor wafer having embedded electroplating current paths to provide uniform plating over wafer surface

Physical vapor deposition methods for forming hydrogen-stuffed trench liners for copper-based metallization

Dual damascene interconnection with metal-insulator-metal-capacitor and method of fabricating the same

Interconnections having double capping layer and method for forming the same

Void-free metal interconnection structure and method of forming the same

Method for forming a dual damascene wiring pattern in a semiconductor device

Method for forming metal wiring layer of semiconductor device

Method of forming metal interconnection layer of semiconductor device

Inter-metal dielectric patterns and method of forming the same

Method of forming dual damascene metal interconnection employing sacrificial metal oxide layer

Structure of a CMOS image sensor and method for fabricating the same

Semiconductor device and methods of forming the same

Interconnections having double capping layer and method for forming the same

Semiconductor device with multi-layered wiring and method for fabricating the same

Method of forming dual damascene interconnection using low-k dielectric material

User terminal device and method for recognizing user&#39;S location using sensor-based behavior recognition

Method of fabricating dual damascene interconnections of microelectronic device using diffusion barrier layer against base material

Methods of forming CMOS integrated circuits that utilize insulating layers with high stress characteristics to improve NMOS and PMOS transistor carrier mobilities

Dual damascene interconnection with metal-insulator-metal capacitor and method of fabricating

Methods of forming dual-damascene interconnect structures on semiconductor substrates using multiple planarization layers having different porosity characteristics

Method of fabricating semiconductor devices having low dielectric interlayer insulation layer

CMOS integrated circuit devices having stressed NMOS and PMOS channel regions therein

Method for forming interconnection line in semiconductor device and interconnection line structure

Integrated circuit capacitor structure

Methods of forming integrated circuit devices having metal interconnect structures therein

Method of forming interconnection lines for semiconductor device

Dual damascene process

Methods for forming contacts for dual stress liner CMOS semiconductor devices

Washing machine

Methods of forming insulation layer patterns and methods of manufacturing semiconductor devices including insulation layer patterns

LEE KYOUNG-WOO

Methods of forming wiring structures

Wiring structures

Monitoring test element groups (TEGs) for etching process and methods of manufacturing a semiconductor device using the same

Methods for fabricating semiconductor devices using liner layers to avoid damage to underlying patterns

LG ELECTRONICS INC

Apparatus and method for providing file structure for multimedia streaming service

Method for deciding network manager in home network

SAMSUNG ELECRTONICS CO LTD

Interconnections having double capping layer and method for forming the same

KIM JUN JUNG

Wiring structures and semiconductor devices

PARK YOUNG HWAN

Absorbable bulky multi-filament draw textured yarn, manufacturing method thereof and medical use using them

User terminal device and method for recognizing user'S location using sensor-based behavior recognition