Inventor

REZNICEK ALEXANDER

US1,303 patents

⚠️ This page may combine multiple inventors who share the name “REZNICEK ALEXANDER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

REZNICEK ALEXANDER

IBM

Stacked complementary FETs featuring vertically stacked horizontal nanowires

Fabrication of nano-sheet transistors with different threshold voltages

Gate-all-around nanowire MOSFET and method of formation

Reduced resistance SiGe FinFET devices and method of forming same

CMOS on hybrid substrate with different crystal orientations using silicon-to-silicon direct wafer bonding

Stacked field-effect transistors (FETs) with shared and non-shared gates

Nanosheet substrate isolated source/drain epitaxy by dual bottom spacer

Gate metal patterning for tight pitch applications

Self-aligned air gap spacer for nanosheet CMOS devices

High acceptor level doping in silicon germanium

Vertical field effect transistor with wrap around metallic bottom contact to improve contact resistance

Contact formation to 3D monolithic stacked FinFETs

Fabrication of strained vertical P-type field effect transistors by bottom condensation

Replacement III-V or germanium nanowires by unilateral confined epitaxial growth

Multiple gate length vertical field-effect-transistors

Channel-last replacement metal-gate vertical field effect transistor

Vertical transistor with air gap spacers

Dual work function integration for stacked FinFET

Method and structure for improving finFET with epitaxy source/drain

Sidewall image transfer process for fin patterning

Method of fabricating electrostatically enhanced fins and stacked nanowire field effect transistors

Method of co-integration of strained silicon and strained germanium in semiconductor devices including fin structures

Gate-all-around nanowire MOSFET and method of formation

Doping of FinFET structures

Mixed orientation and mixed material semiconductor-on-insulator wafer

Strained silicon CMOS on hybrid crystal orientations

Air gap spacer between contact and gate region

Ion implantation combined with in situ or ex situ heat treatment for improved field effect transistors

Stacked field effect transistors with reduced coupling effect

Stacked nanosheet 4T2R unit cell for neuromorphic computing

Nanosheet with selective dipole diffusion into high-k

I/O device for gate-all-around transistors

Nanosheet electrostatic discharge structure

Lateral bipolar junction transistor with controlled junction

Multiple dielectrics for gate-all-around transistors

Faceted sidewall magnetic tunnel junction structure

Full air-gap spacers for gate-all-around nanosheet field effect transistors

Stacked vertical transport field effect transistor electrically erasable programmable read only memory (EEPROM) devices

Vertically stacked NFETS and PFETS with gate-all-around structure

Enhanced field bipolar resistive RAM integrated with FDSOI technology

Stacked nanosheet field effect transistor floating-gate EEPROM cell and array

High-density field-enhanced ReRAM integrated with vertical transistors

Self-aligned air gap spacer for nanosheet CMOS devices

Vertical transport field-effect transistor including dual layer top spacer

Nano-sheet transistors with different threshold voltages

Vertical field effect transistor with abrupt extensions at a bottom source/drain structure

Diode connected vertical transistor

Programmable read only memory (ROM) integrated in tight pitch vertical transistor structures

Tight pitch inverter using vertical transistors

INTERNAT MACHINES CORP

Formation of SOI by oxidation of silicon with engineered porosity gradient