Inventor

VAN DER STRATEN OSCAR

US152 patents

⚠️ This page may combine multiple inventors who share the name “VAN DER STRATEN OSCAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

VAN DER STRATEN OSCAR

IBM

Structure and method for metal integration

Faceted sidewall magnetic tunnel junction structure

Dual metal interconnect structure

Salicide bottom contacts

Selective gate contact fill metallization

Multilayer buried metal-insultor-metal capacitor structures

Bipolar junction transistor (BJT) for liquid flow biosensing applications without a reference electrode and large sensing area

Binary metallization structure for nanoscale dual damascene interconnects

Biconvex low resistance metal wire

Deep high capacity capacitor for bulk substrates

Programmable buried antifuse

Low resistance seed enhancement spacers for voidless interconnect structures

Multi-level metallization interconnect structure

Vertically stacked FinFET fuse

Metal cap protection layer for gate and contact metallization

Epitaxial semiconductor fuse for FinFET structure

Reliable via contact interconnect structure

Low resistivity wrap-around contacts

Magneto-resistive random access memory with laterally-recessed free layer

Physical unclonable function for MRAM structures

Interconnects with enlarged contact area

Laser anneal for MRAM encapsulation enhancement

Interconnects having air gap spacers

Hardmask stress, grain, and structure engineering for advanced memory applications

Buried MIM capacitor structure with landing pads

Programmable buried antifuse

ReRAM structure formed by a single process

Binary metallization structure for nanoscale dual damascene interconnects

Method of forming a dual metal interconnect structure

Salicide bottom contacts

Single process for liner and metal fill

High performance middle of line interconnects

Reflow enhancement layer for metallization structures

High aspect ratio contact metallization without seams

Programmable bulk FinFET antifuses

Vertically stacked FinFET fuse

FinFET resistor and method to fabricate same

Metal FinFET anti-fuse

High performance middle of line interconnects

Structure and method to reduce copper loss during metal cap formation

Thin low defect relaxed silicon germanium layers on bulk silicon substrates

Method of forming dielectric with air gaps for use in semiconductor devices

Copper wiring structures with copper titanium encapsulation

Reflow enhancement layer for metallization structures

Metal-insulator-metal capacitor fabrication with unitary sputtering process

Ion flow barrier structure for interconnect metallization

Metal-insulator-metal capacitor fabrication with unitary sputtering process

Low resistivity wrap-around contacts

YANG CHIH-CHAO

Interconnect structure containing non-damaged dielectric and a via gouging feature

GLOBALFOUNDRIES INC

Devices and methods of cobalt fill metallization