Inventor

ADUSUMILLI PRANEET

US153 patents

⚠️ This page may combine multiple inventors who share the name “ADUSUMILLI PRANEET”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ADUSUMILLI PRANEET

IBM

Recessed metal liner contact with copper fill

Faceted sidewall magnetic tunnel junction structure

Sacrificial cap for forming semiconductor contact

Low resistance dual liner contacts for Fin Field-Effect Transistors (FinFETs)

Dual metal interconnect structure

Salicide bottom contacts

Selective gate contact fill metallization

Multilayer buried metal-insultor-metal capacitor structures

Binary metallization structure for nanoscale dual damascene interconnects

Biconvex low resistance metal wire

Deep high capacity capacitor for bulk substrates

Programmable buried antifuse

Low resistance seed enhancement spacers for voidless interconnect structures

Low resistance source/drain contacts for complementary metal oxide semiconductor (CMOS) devices

Multi-level metallization interconnect structure

Dual silicide liner flow for enabling low contact resistance

Vertically stacked FinFET fuse

Metal cap protection layer for gate and contact metallization

Epitaxial semiconductor fuse for FinFET structure

Recessed metal liner contact with copper fill

Low resistivity wrap-around contacts

Decoupling capacitor inside gate cut trench

Phase-change memory device with reduced programming voltage

Late gate cut with optimized contact trench size

Low resistance source-drain contacts using high temperature silicides

Thermally stable salicide formation for salicide first contacts

Forming thermally stable salicide for salicide first contacts

Intercalation cells for multi-task learning

Paired intercalation cells for drift migration

Low resistance source-drain contacts using high temperature silicides

Low resistance source-drain contacts using high temperature silicides

Forming thermally stable salicide for salicide first contacts

Buried MIM capacitor structure with landing pads

Programmable buried antifuse

Thermally stable salicide formation for salicide first contacts

ReRAM structure formed by a single process

Sacrificial cap for forming semiconductor contact

Binary metallization structure for nanoscale dual damascene interconnects

Method of forming a dual metal interconnect structure

Salicide bottom contacts

Single process for liner and metal fill

High performance middle of line interconnects

Low resistance source/drain contacts for complementary metal oxide semiconductor (CMOS) devices

Reflow enhancement layer for metallization structures

High aspect ratio contact metallization without seams

Programmable bulk FinFET antifuses

Vertically stacked FinFET fuse

FinFET resistor and method to fabricate same

Metal FinFET anti-fuse

GLOBALFOUNDRIES INC

Devices and methods of cobalt fill metallization