Inventor

HSU MENG-KAI

TW33 patents

⚠️ This page may combine multiple inventors who share the name “HSU MENG-KAI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

HSU MENG-KAI

TAIWAN SEMICONDUCTOR MFG CO LTD

Rule checking for multiple patterning technology

Method for legalizing mixed-cell height standard cells of IC

Method of decomposing a layout for multiple-patterning lithography

Method of decomposing a layout for multiple-patterning lithography

Method for triple-patterning friendly placement

Method of analyzing and detecting critical cells

Method and system of generating a layout diagram

Method and system of revising a layout diagram

Method and system for generating layout diagram including wiring arrangement

System and method for generating layout diagram including wiring arrangement

Integrated circuit device and method

Method of analyzing and detecting critical cells

System for generating layout diagram including wiring arrangement

Method for generating layout diagram including wiring arrangement

Method of decomposing a layout for multiple-patterning lithography

Method and system of generating a layout diagram

Semiconductor apparatus including uncrowned and crowned cells and method of making

Method for generating routing structure of semiconductor device

Rule checking for multiple patterning technology

Systems and methods for using multiple libraries with different cell pre-coloring

Rule checking for confining waveform induced constraint variation in static timing analysis

Method of reconfiguring uncrowned standard cells and semiconductor apparatus including uncrowned and crowned cells

Method of reconfiguring uncrowned standard cells and semiconductor apparatus including uncrowned and crowned cells

Semiconductor device and method and system of arranging patterns of the same

Routing structure of semiconductor device and forming method thereof

Method for legalizing mixed-cell height standard cells of IC

Method, device and computer program product for integrated circuit layout generation

Standard cell characterization for internal conductive line of cell

Layout checking method for advanced double patterning photolithography with multiple spacing criteria

TAIWAN SEMICONDUCTOR MFG

Generating database for cells routable in pin layer

Routing method

BALABANOV VALERIY

Method of analytical placement with weighted-average wirelength model

HSU MENG-KAI

Hierarchy-based analytical placement method capable of macro rotation within an integrated circuit