Inventor
KARIAT VINOD
US19 patents
⚠️ This page may combine multiple inventors who share the name “KARIAT VINOD”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
KARIAT VINOD
8 patentsUS8516420B1Aug 20, 2013
Sensitivity and static timing analysis for integrated circuit designs using a multi-CCC current source model
KARIAT VINOD19 citations92
US8103996B2Jan 24, 2012
Method and apparatus for thermal analysis of through-silicon via (TSV)
KARIAT VINOD21 citations91
US8631369B1Jan 14, 2014
Methods, systems, and apparatus for timing and signal integrity analysis of integrated circuits with semiconductor process variations
KARIAT VINOD10 citations83
US8104006B2Jan 24, 2012
Method and apparatus for thermal analysis
KARIAT VINOD13 citations83
US8504958B2Aug 6, 2013
Method and apparatus for thermal analysis
KARIAT VINOD8 citations82
US8104007B2Jan 24, 2012
Method and apparatus for thermal analysis
KARIAT VINOD9 citations82
US8533644B1Sep 10, 2013
Multi-CCC current source models and static timing analysis methods for integrated circuit designs
KARIAT VINOD3 citations62
US8543952B2Sep 24, 2013
Method and apparatus for thermal analysis of through-silicon via (TSV)
KARIAT VINOD4 citations61
CADENCE DESIGN SYSTEMS INC
6 patentsUS7882471B1Feb 1, 2011
Timing and signal integrity analysis of integrated circuits with semiconductor process variations
CADENCE DESIGN SYSTEMS INC56 citations97
US6836873B1Dec 28, 2004
Static noise analysis with noise window estimation and propagation
CADENCE DESIGN SYSTEMS INC19 citations91
US9129078B1Sep 8, 2015
Static timing analysis of integrated circuit designs with flexible noise and delay models of circuit stages
CADENCE DESIGN SYSTEMS INC14 citations84
US8966421B1Feb 24, 2015
Static timing analysis methods for integrated circuit designs using a multi-CCC current source model
CADENCE DESIGN SYSTEMS INC8 citations84
US7900166B2Mar 1, 2011
Method to produce an electrical model of an integrated circuit substrate and related system and article of manufacture
CADENCE DESIGN SYSTEMS INC16 citations82
US7877713B2Jan 25, 2011
Method and apparatus for substrate noise analysis using substrate tile model and tile grid
CADENCE DESIGN SYSTEMS INC4 citations60
PRAMONO EDDY
3 patentsKELLER IGOR
2 patentsUS8595669B1Nov 26, 2013
Flexible noise and delay modeling of circuit stages for static timing analysis of integrated circuit designs
KELLER IGOR39 citations93
US8543954B1Sep 24, 2013
Concurrent noise and delay modeling of circuit stages for static timing analysis of integrated circuit designs
KELLER IGOR28 citations92