Inventor

GHAI SANJEEV

US65 patents

⚠️ This page may combine multiple inventors who share the name “GHAI SANJEEV”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GHAI SANJEEV

IBM

Streaming reads for early processing in a cascaded memory subsystem with buffered memory devices

Streaming reads for early processing in a cascaded memory subsystem with buffered memory devices

Data processing system, cache, and method that select a castout victim in response to the latencies of memory copies of cached data

Multiprocessor system bus protocol for O state memory-consistent data

Multiprocessor system bus with a data-less castout mechanism

Method and system for supplier-based memory speculation in a memory subsystem of a data processing system

Data processing system, cache, and method that utilize a coherency state to indicate the latency of cached data

Data processing system, cache, and method of cache management including an O state for memory-consistent cache lines

Method of cache management for dynamically disabling O state memory-consistent data

Data processing system and method for efficient storage of metadata in a system memory

Data cache block deallocate requests in a multi-level cache hierarchy

Adaptive memory access speculation

Data processing system and method of communication that employ a request-and-forget protocol

Method and system of managing virtualized physical memory in a data processing system

Method and system of managing virtualized physical memory in a memory controller and processor system

Method and system of managing virtualized physical memory in a multi-processor system

Method and apparatus for allocating data usages within an embedded dynamic random access memory device

System for dynamically selecting maximum number of accessible banks of memory per cycle by monitoring actual power to each of the banks to determine the number of accessible banks

High performance mechanism to support O state horizontal cache-to-cache transfers

Cache configured to log addresses of high-availability data via a non-blocking channel

Double DRAM bit steering for multiple error corrections

Double DRAM bit steering for multiple error corrections

Efficient storage of metadata in a system memory

Data processing system having no system memory

Method and system for high speed access to a banked cache memory

Apparatus for associating cache memories with processors within a multiprocessor data processing system

Method and apparatus for forwarding data in a hierarchial cache memory architecture

Dynamic mechanism to upgrade o state memory-consistent cache lines

Synchronizing access to shared memory by extending protection for a target address of a store-conditional request

Synchronized access to shared memory by extending protection for a store target address of a store-conditional request

Virtual machine failover

Data processing system and method for handling castout collisions

Information handling system with immediate scheduling of load operations

Bypassing a store-conditional request around a store queue

Virtual machines failover

Data cache block deallocate requests

Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers that uses dynamic hardware/software controls

Method and apparatus for concurrently communicating with multiple embedded dynamic random access memory devices

Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers performing directory update

Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers

Method and apparatus for a data-less write operation within a cache memory hierarchy for a data processing system

Prefetch unit filter for microprocessor

Dynamic transaction throttling in a data processing system supporting transactional memory

Accelerated processing of streams of load-reserve requests

Synchronized access to data in shared memory by protecting the load target address of a fronting load

Banked cache temporarily favoring selection of store requests from one of multiple store queues

GHAI SANJEEV

Data cache block deallocate requests

Information handling system with immediate scheduling of load operations

ARIMILLI RAVI KUMAR

Method and system for thread-based memory speculation in a memory subsystem of a data processing system

GLOBALFOUNDRIES INC

Management of transactional memory access requests by a cache memory