P

Inventor

NA MYUNG-HEE

US26 patents
⚠️ This page may combine multiple inventors who share the name “NA MYUNG-HEE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

IBM

22 patents
US9735029B1Aug 15, 2017

Metal fill optimization for self-aligned double patterning

IBM22 citations93
US8928086B2Jan 6, 2015

Strained finFET with an electrically isolated channel

IBM19 citations93
US8354309B2Jan 15, 2013

Method of providing threshold voltage adjustment through gate dielectric stack modification

IBM24 citations92
US7011980B1Mar 14, 2006

Method and structures for measuring gate tunneling leakage parameters of field effect transistors

IBM34 citations92
US10892331B2Jan 12, 2021

Channel orientation of CMOS gate-all-around field-effect transistor devices for enhanced carrier mobility

IBM9 citations86
US9190520B2Nov 17, 2015

Strained finFET with an electrically isolated channel

IBM15 citations84
US9171935B2Oct 27, 2015

FinFET formation with late fin reveal

IBM9 citations83
US10833267B2Nov 10, 2020

Structure and method to form phase change memory cell with self- align top electrode contact

IBM3 citations73
US9029913B2May 12, 2015

Silicon-germanium fins and silicon fins on a bulk substrate

IBM5 citations73
US10614877B1Apr 7, 2020

4T static random access memory bitcell retention

IBM3 citations71
US10381068B2Aug 13, 2019

Ultra dense and stable 4T SRAM cell design having NFETs and PFETs

IBM4 citations71
US11101367B2Aug 24, 2021

Contact-first field-effect transistors

IBM0 citations62
US10937961B2Mar 2, 2021

Structure and method to form bi-layer composite phase-change-memory cell

IBM1 citations62
US10424574B2Sep 24, 2019

Standard cell architecture with at least one gate contact over an active area

IBM1 citations62
US10693005B2Jun 23, 2020

Reliable gate contacts over active areas

IBM1 citations60
US10803933B2Oct 13, 2020

Self-aligned high density and size adjustable phase change memory

IBM0 citations52
US10424576B2Sep 24, 2019

Standard cell architecture with at least one gate contact over an active area

IBM0 citations52
US8648647B2Feb 11, 2014

Determining current of a first FET of body connected FETs

IBM0 citations52
US7795098B1Sep 14, 2010

Rotated field effect transistors and method of manufacture

IBM0 citations52
US7335563B2Feb 26, 2008

Rotated field effect transistors and method of manufacture

IBM0 citations52
US10381338B2Aug 13, 2019

Metal fill optimization for self-aligned double patterning

IBM0 citations51
US8032349B2Oct 4, 2011

Efficient methodology for the accurate generation of customized compact model parameters from electrical test data

IBM0 citations37

GREENE BRIAN J

1 patent

INT BUSNIESS MACHINES CORPORATION

1 patent

NA MYUNG-HEE

1 patent

GLOBALFOUNDRIES INC

1 patent