Inventor
TOPACIO RODEN
CA15 patents
⚠️ This page may combine multiple inventors who share the name “TOPACIO RODEN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
TOPACIO RODEN
8 patentsUS8227926B2Jul 24, 2012
Routing layer for mitigating stress in a semiconductor die
TOPACIO RODEN28 citations90
US9059159B2Jun 16, 2015
Routing layer for mitigating stress in a semiconductor die
TOPACIO RODEN6 citations82
US8299632B2Oct 30, 2012
Routing layer for mitigating stress in a semiconductor die
TOPACIO RODEN9 citations82
US8313984B2Nov 20, 2012
Die substrate with reinforcement structure
TOPACIO RODEN4 citations59
US10431533B2Oct 1, 2019
Circuit board with constrained solder interconnect pads
TOPACIO RODEN1 citations52
US8633599B2Jan 21, 2014
Semiconductor chip with underfill anchors
TOPACIO RODEN0 citations51
US8642463B2Feb 4, 2014
Routing layer for mitigating stress in a semiconductor die
TOPACIO RODEN0 citations50
US8927344B2Jan 6, 2015
Die substrate with reinforcement structure
TOPACIO RODEN1 citations48
ATI TECHNOLOGIES ULC
5 patentsUS7985621B2Jul 26, 2011
Method and apparatus for making semiconductor packages
ATI TECHNOLOGIES ULC8 citations83
US11942405B2Mar 26, 2024
Semiconductor package assembly using a passive device as a standoff
ATI TECHNOLOGIES ULC1 citations62
US12148715B2Nov 19, 2024
Electronic device including a substrate, a structure, and an adhesive and a process of forming the same
ATI TECHNOLOGIES ULC0 citations61
US9035471B2May 19, 2015
Routing layer for mitigating stress in a semiconductor die
ATI TECHNOLOGIES ULC3 citations61
US8664777B2Mar 4, 2014
Routing layer for mitigating stress in a semiconductor die
ATI TECHNOLOGIES ULC3 citations61