Inventor

ELDREDGE KENNETH J

US64 patents

⚠️ This page may combine multiple inventors who share the name “ELDREDGE KENNETH J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ELDREDGE KENNETH J

MICRON TECHNOLOGY INC

Neural network in a memory device

Methods for pattern matching using multiple cell pairs

Memory device having a controller to enable and disable mode control circuitry of the controller

Methods and apparatus for pattern matching using redundant memory elements

Memory as a programmable logic device

Memory devices configured to apply different weights to different strings of memory cells coupled to a data line and methods

Methods and apparatus for pattern matching having memory cell pairs coupled in series and coupled in parallel

Memory devices for comparing input data to data stored in memory cells coupled to a data line

Memory devices for pattern matching based on majority of cell pair match

Memory devices for pattern matching

Memory configured to perform logic operations on values representative of sensed characteristics of data lines and a threshold data value

Methods and apparatus for pattern matching in a memory containing sets of memory elements

Methods of operating a memory device comparing input data to data stored in memory cells coupled to a data line

Memory devices configured to apply different weights to different strings of memory cells coupled to a data line and methods

Methods of operating a memory device comparing input data to data stored in memory cells coupled to a data line

Memory configured to generate a data value from a data line connected to more than one string of series-connected memory cells

Configurable operating mode memory device and methods of operation

Methods of operating a memory device comparing input data to data stored in memory cells coupled to a data line

Memory as a programmable logic device

HEWLETT PACKARD DEVELOPMENT CO

Self-testing of magneto-resistive memory arrays

Triple sample sensing for magnetic random access memory (MRAM) with series diodes

Hybrid data I/O for memory applications

Multiple logical bits per memory cell in a memory device

Packaging for storage devices using electron emissions

MRAM having two write conductors

Magnetic memory device

System having a storage controller that modifies operation of a storage system based on the status of a data transfer

Connection arrangements for electrical devices

Self-healing MRAM

Systems for controlling storage device emitters

Atomic resolution storage device configured as a redundant array of independent storage devices

Assisted memory system

Storage device having a probe to form structures for representing data states

MRAM having two write conductors

Multiple buffer memory interface

Accelerometer using field emitter technology

Systems and methods for translating voltage levels of digital signals

HEWLETT PACKARD CO

Write circuit for large MRAM arrays

Reference signal generation for magnetic random access memory devices

MRAM device including digital sense amplifiers

Reference signal generation for magnetic random access memory devices

Operational amplifier with digital offset calibration

Write circuit for large MRAM arrays

Continuous antifuse material in memory structure

ELDREDGE KENNETH J

Solid state storage element and method

Interpreting the data value stored by memory cell using a performance characteristic value

HEWLETT PACKARD COMPANY L P

Triple sample sensing for magnetic random access memory (MRAM) with series diodes

BENHOV GMBH LLC

Memory configuration and method for calibrating read/write data based on performance characteristics of the memory configuration

SAMSUNG ELECTRONICS CO INC

Integrated circuit memory devices with MRAM voltage divider strings therein

SAMSUNG ELECTRONICS CO LTD

Increased magnetic memory array sizes and operating margins