Inventor
KULKARNI NIRANJAN
US9 patents
⚠️ This page may combine multiple inventors who share the name “KULKARNI NIRANJAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
VRUDHULA SARMA
7 patentsUS9876503B2Jan 23, 2018
Method of obfuscating digital logic circuits using threshold voltage
VRUDHULA SARMA16 citations82
US9473139B2Oct 18, 2016
Threshold logic element with stabilizing feedback
VRUDHULA SARMA7 citations82
US9356598B2May 31, 2016
Threshold logic gates with resistive networks
VRUDHULA SARMA8 citations82
US8832614B2Sep 9, 2014
Technology mapping for threshold and logic gate hybrid circuits
VRUDHULA SARMA13 citations82
US10551869B2Feb 4, 2020
Clock skewing strategy to reduce dynamic power and eliminate hold-time violations in synchronous digital VLSI designs
VRUDHULA SARMA5 citations71
US10447249B2Oct 15, 2019
Hold violation free scan chain and scanning mechanism for testing of synchronous digital VLSI circuits
VRUDHULA SARMA4 citations71
US10250236B2Apr 2, 2019
Energy efficient, robust differential mode d-flip-flop
VRUDHULA SARMA5 citations71