Inventor

SURESH VIKRAM

US31 patents

⚠️ This page may combine multiple inventors who share the name “SURESH VIKRAM”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SURESH VIKRAM

INTEL CORP

Apparatuses and methods for frequency scaling a message scheduler data path of a hashing accelerator

Unified accelerator for classical and post-quantum digital signature schemes in computing environments

Low latency post-quantum signature verification for fast secure-boot

Combined SHA2 and SHA3 based XMSS hardware accelerator

Accelerators for post-quantum cryptography secure hash-based signing and verification

Unified AES-SMS4—Camellia symmetric key block cipher acceleration

Physically unclonable function with feed-forward addressing and variable latency output

Device, system, and method to change a consistency of behavior by a cell circuit

Bitcoin mining hardware accelerator with optimized message digest and message scheduler datapath

Hardware accelerators and methods for high-performance authenticated encryption

Hardware accelerator for platform firmware integrity check

Techniques for secure authentication

Hybrid AES-SMS4 hardware accelerator

Compact, low power advanced encryption standard circuit

Fine-grained bitcoin engine deactivation for yield recovery, performance, and/or power management

Low latency post-quantum signature verification for fast secure-boot

Combined SHA2 and SHA3 based XMSS hardware accelerator

Secure PUF-based device authentication using adversarial challenge selection

Accelerators for post-quantum cryptography secure hash-based signing and verification

Odd index precomputation for authentication path computation

Message index aware multi-hash accelerator for post quantum cryptography secure hash-based signing and verification

Technology for generating a keystream while combatting side-channel attacks

Fast XMSS signature verification and nonce sampling process without signature expansion

Secure PUF-based device authentication using adversarial challenge selection

Message index aware multi-hash accelerator for post quantum cryptography secure hash-based signing and verification

Odd index precomputation for authentication path computation

Post quantum public key signature operation for reconfigurable circuit devices

Apparatus and method for generating hybrid static/dynamic entropy physically unclonable function

Self-calibrated von-neumann extractor

Time and frequency domain side-channel leakage suppression using integrated voltage regulator cascaded with runtime crypto arithmetic transformations

SCHREIBER RUSSELL

Memory access control system and method