Inventor

MATHEW SANU

US41 patents

⚠️ This page may combine multiple inventors who share the name “MATHEW SANU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MATHEW SANU

INTEL CORP

Apparatuses and methods for frequency scaling a message scheduler data path of a hashing accelerator

Boosted multiplexer transmission gate

SMS4 acceleration hardware

Reconfigurable SIMD vector processing system

Unified accelerator for classical and post-quantum digital signature schemes in computing environments

Low latency post-quantum signature verification for fast secure-boot

Combined SHA2 and SHA3 based XMSS hardware accelerator

Accelerators for post-quantum cryptography secure hash-based signing and verification

Unified AES-SMS4—Camellia symmetric key block cipher acceleration

Physically unclonable function with feed-forward addressing and variable latency output

Device, system, and method to change a consistency of behavior by a cell circuit

Bitcoin mining hardware accelerator with optimized message digest and message scheduler datapath

Hardware accelerators and methods for high-performance authenticated encryption

Variable format, variable sparsity matrix multiplication instruction

Hardware accelerator for platform firmware integrity check

Techniques for secure authentication

Hybrid AES-SMS4 hardware accelerator

Compact, low power advanced encryption standard circuit

Modular multiplication acceleration circuit and method for data encryption/decryption

Fine-grained bitcoin engine deactivation for yield recovery, performance, and/or power management

Low latency post-quantum signature verification for fast secure-boot

Combined SHA2 and SHA3 based XMSS hardware accelerator

Accelerators for post-quantum cryptography secure hash-based signing and verification

Odd index precomputation for authentication path computation

Secure PUF-based device authentication using adversarial challenge selection

Message index aware multi-hash accelerator for post quantum cryptography secure hash-based signing and verification

Technology for generating a keystream while combatting side-channel attacks

Secure PUF-based device authentication using adversarial challenge selection

Message index aware multi-hash accelerator for post quantum cryptography secure hash-based signing and verification

Odd index precomputation for authentication path computation

Post quantum public key signature operation for reconfigurable circuit devices

Apparatus and method for generating hybrid static/dynamic entropy physically unclonable function

Self-calibrated von-neumann extractor

Native composite-field AES encryption/decryption accelerator circuit

Side-channel resistant multiplicatively masked encryption engine with zero-value attack detection

Time and frequency domain side-channel leakage suppression using integrated voltage regulator cascaded with runtime crypto arithmetic transformations

Simon-based hashing for fuse validation

SATPATHY SUDHIR

Priority-based routing

ANDERS MARK

Method and apparatus for video processing

MATHEW SANU

Multiplier product generation based on encoded data from addressable location

SHEIKH FARHANA

Graphics lighting engine including log and anti-log units