Inventor

UPASANI NEERAJ

US20 patents

⚠️ This page may combine multiple inventors who share the name “UPASANI NEERAJ”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

UPASANI NEERAJ

META PLATFORMS TECH LLC

System on a chip (SoC) communications to prevent direct memory access (DMA) attacks

Tamper detection and prevention in computer systems having one-time programmable memory

ROM instruction authentication and integrity verification for artificial reality security controller

Inline encryption of packet data in a wireless communication system

Wireless communication with code separation

Parallel scheduling of encryption engines and decryption engines to prevent side channel attacks

Artificial reality system with multi-stage boot process

Artificial reality system with inter-processor communication (IPC)

System on a chip (SOC) communications to prevent direct memory access (DMA) attacks

Distributed phased SRAM repair for systems on a chip

Isolation of secrets from an operating system

High throughput storage encryption

FACEBOOK TECH LLC

Inline encryption of packet data in a wireless communication system

Multi-key encryption and decryption for side channel attack prevention

Monitoring circuit including cascaded s-boxes for fault injection attack protection

Randomized clock cycle lengths for boot sequences

Swapping of encryption and decryption operations for side channel attack protection

Mixed sequencing of polynomial-diverse encryption and decryption operations for side channel attack protection

INTEL CORP

Hardware accelerator for platform firmware integrity check

Protected runtime mode