P

Inventor

GLASS GLENN

US21 patents
⚠️ This page may combine multiple inventors who share the name “GLASS GLENN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

19 patents
US7678631B2Mar 16, 2010

Formation of strain-inducing films

INTEL CORP22 citations92
US11527612B2Dec 13, 2022

Gate-all-around integrated circuit structures having vertically discrete source or drain structures

INTEL CORP6 citations74
US11515407B2Nov 29, 2022

High breakdown voltage structure for high performance GaN-based HEMT and MOS devices to enable GaN C-MOS

INTEL CORP2 citations73
US10672868B2Jun 2, 2020

Methods of forming self aligned spacers for nanowire device structures

INTEL CORP4 citations72
US10573750B2Feb 25, 2020

Methods of forming doped source/drain contacts and structures formed thereby

INTEL CORP2 citations72
US10396201B2Aug 27, 2019

Methods of forming dislocation enhanced strain in NMOS structures

INTEL CORP1 citations71
US12255234B2Mar 18, 2025

Integrated circuit structures having germanium-based channels

INTEL CORP0 citations62
US12206027B2Jan 21, 2025

Gate-all-around integrated circuit structures having nanowires with tight vertical spacing

INTEL CORP0 citations62
US11923421B2Mar 5, 2024

Integrated circuit structures having germanium-based channels

INTEL CORP0 citations62
US11769836B2Sep 26, 2023

Gate-all-around integrated circuit structures having nanowires with tight vertical spacing

INTEL CORP1 citations62
US11450739B2Sep 20, 2022

Germanium-rich nanowire transistor with relaxed buffer layer

INTEL CORP0 citations62
US11437472B2Sep 6, 2022

Integrated circuit structures having germanium-based channels

INTEL CORP0 citations62
US11004978B2May 11, 2021

Methods of forming doped source/drain contacts and structures formed thereby

INTEL CORP0 citations62
US11411110B2Aug 9, 2022

Methods of forming dislocation enhanced strain in NMOS and PMOS structures

INTEL CORP0 citations61
US11107920B2Aug 31, 2021

Methods of forming dislocation enhanced strain in NMOS structures

INTEL CORP0 citations61
US12484266B2Nov 25, 2025

Gate-all-around integrated circuit structures having underlying dopant-diffusion blocking layers

INTEL CORP0 citations59
US11469299B2Oct 11, 2022

Gate-all-around integrated circuit structures having underlying dopant-diffusion blocking layers

INTEL CORP0 citations59
US10644112B2May 5, 2020

Systems, methods and devices for isolation for subfin leakage

INTEL CORP0 citations52
US12414366B2Sep 9, 2025

Co-integration of high voltage (HV) and low voltage (LV) transistor structures, using channel height and spacing modulation

INTEL CORP0 citations50

DAEDALUS PRIME LLC

2 patents