Inventor

JAMBUNATHAN KARTHIK

US44 patents

Patents

44 patents

US10734412B2Aug 4, 2020

Backside contact resistance reduction for semiconductor devices with metallization on both sides

INTEL CORP15 citations86

US11222977B2Jan 11, 2022

Source/drain diffusion barrier for germanium NMOS transistors

INTEL CORP8 citations85

US11251302B2Feb 15, 2022

Epitaxial oxide plug for strained transistors

INTEL CORP2 citations73

US10892337B2Jan 12, 2021

Backside source/drain replacement for semiconductor devices with metallization on both sides

INTEL CORP2 citations73

US10373977B2Aug 6, 2019

Techniques for forming transistors on the same die with varied channel materials

INTEL CORP4 citations72

US11101268B2Aug 24, 2021

Transistors employing non-selective deposition of source/drain material

INTEL CORP2 citations70

US11121030B2Sep 14, 2021

Transistors employing carbon-based etch stop layer for preserving source/drain material during contact trench etch

INTEL CORP0 citations63

US11101350B2Aug 24, 2021

Integrated circuit with germanium-rich channel transistors including one or more dopant diffusion barrier elements

INTEL CORP0 citations63

US11081570B2Aug 3, 2021

Transistors with lattice matched gate structure

INTEL CORP0 citations63

US11004954B2May 11, 2021

Epitaxial buffer to reduce sub-channel leakage in MOS transistors

INTEL CORP0 citations63

US10483353B2Nov 19, 2019

Transistor including tensile-strained germanium channel

INTEL CORP1 citations63

US12419091B2Sep 16, 2025

Source electrode and drain electrode protection for nanowire transistors

INTEL CORP0 citations62

US11757037B2Sep 12, 2023

Epitaxial oxide plug for strained transistors

INTEL CORP0 citations62

US11735670B2Aug 22, 2023

Non-selective epitaxial source/drain deposition to reduce dopant diffusion for germanium NMOS transistors

INTEL CORP0 citations62

US11699756B2Jul 11, 2023

Source/drain diffusion barrier for germanium nMOS transistors

INTEL CORP0 citations62

US11538905B2Dec 27, 2022

Nanowire transistors employing carbon-based layers

INTEL CORP0 citations62

US11444166B2Sep 13, 2022

Backside source/drain replacement for semiconductor devices with metallization on both sides

INTEL CORP1 citations62

US11411096B2Aug 9, 2022

Source electrode and drain electrode protection for nanowire transistors

INTEL CORP0 citations62

US11189730B2Nov 30, 2021

Non-selective epitaxial source/drain deposition to reduce dopant diffusion for germanium nMOS transistors

INTEL CORP0 citations62

US11101356B2Aug 24, 2021

Doped insulator cap to reduce source/drain diffusion for germanium NMOS transistors

INTEL CORP0 citations62

US11011620B2May 18, 2021

Techniques for increasing channel region tensile strain in n-MOS devices

INTEL CORP0 citations62

US11004978B2May 11, 2021

Methods of forming doped source/drain contacts and structures formed thereby

INTEL CORP0 citations62

US10944006B2Mar 9, 2021

Geometry tuning of fin based transistor

INTEL CORP0 citations62

US10879241B2Dec 29, 2020

Techniques for controlling transistor sub-fin leakage

INTEL CORP1 citations62

US10403752B2Sep 3, 2019

Prevention of subchannel leakage current in a semiconductor device with a fin structure

INTEL CORP1 citations62

US11069795B2Jul 20, 2021

Transistors with channel and sub-channel regions with distinct compositions and dimensions

INTEL CORP1 citations61

US11056592B2Jul 6, 2021

Silicon substrate modification to enable formation of thin, relaxed, germanium-based layer

INTEL CORP1 citations60

US11430787B2Aug 30, 2022

Forming crystalline source/drain contacts on semiconductor devices

INTEL CORP0 citations58

US12550401B2Feb 10, 2026

Doped STI to reduce source/drain diffusion for germanium NMOS transistors

INTEL CORP0 citations52

US11588017B2Feb 21, 2023

Nanowire for transistor integration

INTEL CORP0 citations52

US11335600B2May 17, 2022

Integration method for finfet with tightly controlled multiple fin heights

INTEL CORP0 citations52

US11264501B2Mar 1, 2022

Device, method and system for promoting channel stress in a NMOS transistor

INTEL CORP0 citations52

US11024737B2Jun 1, 2021

Etching fin core to provide fin doubling

INTEL CORP0 citations52

US10749032B2Aug 18, 2020

Techniques for forming transistors including group III-V material nanowires using sacrificial group IV material layers

INTEL CORP0 citations52

US10692973B2Jun 23, 2020

Germanium-rich channel transistors including one or more dopant diffusion barrier elements

INTEL CORP0 citations52

US10516021B2Dec 24, 2019

Reduced leakage transistors with germanium-rich channel regions

INTEL CORP0 citations52

US11482457B2Oct 25, 2022

Substrate defect blocking layers for strained channel semiconductor devices

INTEL CORP0 citations51

US10559689B2Feb 11, 2020

Crystallized silicon carbon replacement material for NMOS source/drain regions

INTEL CORP0 citations51

US11404575B2Aug 2, 2022

Diverse transistor channel materials enabled by thin, inverse-graded, germanium-based layer

INTEL CORP0 citations50

US10510848B2Dec 17, 2019

Sub-fin sidewall passivation in replacement channel FinFETS

INTEL CORP0 citations41

JAMBUNATHAN KARTHIK

Patents

Backside contact resistance reduction for semiconductor devices with metallization on both sides

Source/drain diffusion barrier for germanium NMOS transistors

Epitaxial oxide plug for strained transistors

Backside source/drain replacement for semiconductor devices with metallization on both sides

Transistor fin formation via cladding on sacrificial core

Ge/SiGe-channel and III-V-channel transistors on the same die

Methods of forming self aligned spacers for nanowire device structures

Methods of forming doped source/drain contacts and structures formed thereby

Techniques for forming transistors on the same die with varied channel materials

Transistors employing non-selective deposition of source/drain material

Transistors employing carbon-based etch stop layer for preserving source/drain material during contact trench etch

Integrated circuit with germanium-rich channel transistors including one or more dopant diffusion barrier elements

Transistors with lattice matched gate structure

Epitaxial buffer to reduce sub-channel leakage in MOS transistors

Transistor including tensile-strained germanium channel

Source electrode and drain electrode protection for nanowire transistors

Epitaxial oxide plug for strained transistors

Non-selective epitaxial source/drain deposition to reduce dopant diffusion for germanium NMOS transistors

Source/drain diffusion barrier for germanium nMOS transistors

Nanowire transistors employing carbon-based layers

Backside source/drain replacement for semiconductor devices with metallization on both sides

Source electrode and drain electrode protection for nanowire transistors

Non-selective epitaxial source/drain deposition to reduce dopant diffusion for germanium nMOS transistors

Doped insulator cap to reduce source/drain diffusion for germanium NMOS transistors

Techniques for increasing channel region tensile strain in n-MOS devices

Methods of forming doped source/drain contacts and structures formed thereby

Geometry tuning of fin based transistor

Techniques for controlling transistor sub-fin leakage

Prevention of subchannel leakage current in a semiconductor device with a fin structure

Transistors with channel and sub-channel regions with distinct compositions and dimensions

Silicon substrate modification to enable formation of thin, relaxed, germanium-based layer

Forming crystalline source/drain contacts on semiconductor devices

Doped STI to reduce source/drain diffusion for germanium NMOS transistors

Nanowire for transistor integration

Integration method for finfet with tightly controlled multiple fin heights

Device, method and system for promoting channel stress in a NMOS transistor

Etching fin core to provide fin doubling

Techniques for forming transistors including group III-V material nanowires using sacrificial group IV material layers

Germanium-rich channel transistors including one or more dopant diffusion barrier elements

Reduced leakage transistors with germanium-rich channel regions

Substrate defect blocking layers for strained channel semiconductor devices

Crystallized silicon carbon replacement material for NMOS source/drain regions

Diverse transistor channel materials enabled by thin, inverse-graded, germanium-based layer

Sub-fin sidewall passivation in replacement channel FinFETS