Inventor

KIM SEIYON

US81 patents

⚠️ This page may combine multiple inventors who share the name “KIM SEIYON”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KIM SEIYON

INTEL CORP

Nanowire transistor devices and forming techniques

Integration methods to fabricate internal spacers for nanowire devices

Method of preparing active silicon regions for CMOS or other devices

Vertical integration scheme and circuit elements architecture for area scaling of semiconductor devices

CMOS nanowire structure

Nanowire transistor devices and forming techniques

Silicon and silicon germanium nanowire structures

Semiconductor device with isolated body portion

Integration methods to fabricate internal spacers for nanowire devices

Internal spacers for nanowire transistors and method of fabrication thereof

Integration methods to fabricate internal spacers for nanowire devices

Nanowire transistor fabrication with hardmask layers

Uniaxially strained nanowire structure

Leakage reduction structures for nanowire transistors

Nanowire structures having wrap-around contacts

Methods of forming self aligned spacers for nanowire device structures

Methods of forming doped source/drain contacts and structures formed thereby

Offstate parasitic leakage reduction for tunneling field effect transistors

Multilayer insulator stack for ferroelectric transistor and capacitor

Non-planar semiconductor device having hybrid geometry-based active region

Non-planar semiconductor device having hybrid geometry-based active region

Internal spacers for nanowire transistors and method of fabrication thereof

Nanowire transistor with underlayer etch stops

Memory devices based on capacitors with built-in electric field

SONY GROUP CORP

Nanowire transistor fabrication with hardmask layers

Integration methods to fabricate internal spacers for nanowire devices

Silicon and silicon germanium nanowire structures

Nanowire transistor fabrication with hardmask layers

Integration methods to fabricate internal spacers for nanowire devices

Nanowire transistor fabrication with hardmask layers

Integration methods to fabricate internal spacers for nanowire devices

KIM SEIYON

Integration methods to fabricate internal spacers for nanowire devices

CMOS nanowire structure

CMOS nanowire structure

Nanowire transistor with underlayer etch stops

CEA STEPHEN M

Uniaxially strained nanowire structure

Nanowire structures having non-discrete source and drain regions

Nanowire structures having non-discrete source and drain regions

Nanowire structures having wrap-around contacts

GOOGLE LLC

Non-planar semiconductor device having hybrid geometry-based active region

Nanowire structures having non-discrete source and drain regions

Nanowire structures having non-discrete source and drain regions

KUHN KELIN J

Silicon and silicon germanium nanowire structures

Silicon and silicon germanium nanowire structures

CAPPELLANI ANNALISA

Semiconductor device with isolated body portion

Semiconductor devices having modulated nanowire counts

SONY CORP

Nanowire transistor fabrication with hardmask layers

Silicon and silicon germanium nanowire structures

GLASS GLENN A

Nanowire transistor devices and forming techniques

SK HYNIX INC

Semiconductor device and method for fabricating the same