Inventor
LANGER JAN
DE26 patents
Patents
26 patentsUS10866753B2Dec 15, 2020
Data processing engine arrangement in a device
XILINX INC15 citations94
US11336287B1May 17, 2022
Data processing engine array architecture with memory tiles
XILINX INC26 citations93
US10824584B1Nov 3, 2020
Device with data processing engine array that enables partial reconfiguration
XILINX INC13 citations85
US10747690B2Aug 18, 2020
Device with data processing engine array
XILINX INC19 citations85
US11669464B1Jun 6, 2023
Multi-addressing mode for DMA and non-sequential read and write patterns
XILINX INC9 citations84
US11520717B1Dec 6, 2022
Memory tiles in data processing engine array
XILINX INC11 citations84
US9189458B1Nov 17, 2015
Parameter estimation
XILINX INC16 citations84
US10635622B2Apr 28, 2020
System-on-chip interface architecture
XILINX INC10 citations83
US11573726B1Feb 7, 2023
Data processing engine arrangement in a device
XILINX INC1 citations73
US11567881B1Jan 31, 2023
Event-based debug, trace, and profile in device with data processing engine array
XILINX INC2 citations73
US11323391B1May 3, 2022
Multi-port stream switch for stream interconnect network
XILINX INC6 citations73
US11113223B1Sep 7, 2021
Dual mode interconnect
XILINX INC4 citations73
US11379389B1Jul 5, 2022
Communicating between data processing engines using shared memory
XILINX INC2 citations72
US11061673B1Jul 13, 2021
Data selection network for a data processing engine in an integrated circuit
XILINX INC2 citations72
US11016822B1May 25, 2021
Cascade streaming between data processing engines in an array
XILINX INC3 citations72
US10990552B1Apr 27, 2021
Streaming interconnect architecture for data processing engine array
XILINX INC4 citations72
US10747531B1Aug 18, 2020
Core for a data processing engine in an integrated circuit
XILINX INC3 citations72
US10579559B1Mar 3, 2020
Stall logic for a data processing engine in an integrated circuit
XILINX INC2 citations72
US12536132B2Jan 27, 2026
Data processing engine tile architecture for an integrated circuit
XILINX INC0 citations62
US12105667B2Oct 1, 2024
Device with data processing engine array that enables partial reconfiguration
XILINX INC0 citations62
US11972132B2Apr 30, 2024
Data processing engine arrangement in a device
XILINX INC0 citations62
US11853235B2Dec 26, 2023
Communicating between data processing engines using shared memory
XILINX INC0 citations62
US11730325B2Aug 22, 2023
Dual mode interconnect
XILINX INC0 citations62
US11372803B2Jun 28, 2022
Data processing engine tile architecture for an integrated circuit
XILINX INC1 citations62
US11599498B1Mar 7, 2023
Device with data processing engine array that enables partial reconfiguration
XILINX INC0 citations61
US11443091B1Sep 13, 2022
Data processing engines with cascade connected cores
XILINX INC1 citations59