Inventor · disambiguated record
Richard L. Walke
Also filed as: WALKE RICHARD · WALKE RICHARD L · WALKE RICHARD LEWIS
24 granted patents·287 citations·filing 2007–2022
96Inventor score
Top patents by PatentIndex Score
24 records- 0198US11348624B1Shared multi-port memory from single portXILINX INC·Filed 2021·Granted May 31, 2022·7 cites·20 claims
- 0296US10866753B2Data processing engine arrangement in a deviceXILINX INC·Filed 2018·Granted Dec 15, 2020·15 cites·10 claims
- 0396US10747690B2Device with data processing engine arrayXILINX INC·Filed 2018·Granted Aug 18, 2020·19 cites·20 claims
- 0496US9778905B1Multiplier circuits configurable for real or complex operationXILINX INC·Filed 2016·Granted Oct 3, 2017·25 cites·20 claims
- 0596US9081634B1Digital signal processing blockXILINX INC·Filed 2012·Granted Jul 14, 2015·61 cites·9 claims
- 0692US8250342B1Digital signal processing engineKOSTARNOV IGOR·Filed 2008·Granted Aug 21, 2012·60 cites·39 claims
- 0790US8463835B1Circuit for and method of providing a floating-point adderWALKE RICHARD·Filed 2007·Granted Jun 11, 2013·35 cites·18 claims
- 0889US10833704B1Low-density parity check decoder using encoded no-operation instructionsXILINX INC·Filed 2018·Granted Nov 10, 2020·10 cites·20 claims
- 0988US10797727B1Low-density parity-check (LDPC) encode using an LDPC decoderXILINX INC·Filed 2018·Granted Oct 6, 2020·8 cites·20 claims
- 1087US11108410B1User-programmable LDPC decoderXILINX INC·Filed 2018·Granted Aug 31, 2021·7 cites·16 claims
- 1186US10484012B1Systems and methods for decoding quasi-cyclic (QC) low-density parity-check (LDPC) codesXILINX INC·Filed 2017·Granted Nov 19, 2019·7 cites·20 claims
- 1285US10990552B1Streaming interconnect architecture for data processing engine arrayXILINX INC·Filed 2018·Granted Apr 27, 2021·4 cites·20 claims
- 1384US11075650B1Sub-matrix reduction for quasi-cyclic LDPC codesXILINX INC·Filed 2019·Granted Jul 27, 2021·5 cites·20 claims
- 1484US10673564B1Software defined modemXILINX INC·Filed 2018·Granted Jun 2, 2020·5 cites·20 claims
- 1583US11573726B1Data processing engine arrangement in a deviceXILINX INC·Filed 2020·Granted Feb 7, 2023·1 cites·8 claims
- 1682US11082067B1System and method for determining bit types for polar encoding and decodingXILINX INC·Filed 2019·Granted Aug 3, 2021·5 cites·20 claims
- 1782US11016822B1Cascade streaming between data processing engines in an arrayXILINX INC·Filed 2018·Granted May 25, 2021·3 cites·21 claims
- 1877US11972132B2Data processing engine arrangement in a deviceXILINX INC·Filed 2022·Granted Apr 30, 2024·0 cites·19 claims
- 1975US11061673B1Data selection network for a data processing engine in an integrated circuitXILINX INC·Filed 2018·Granted Jul 13, 2021·2 cites·16 claims
- 2075US10727869B1Efficient method for packing low-density parity-check (LDPC) decode operationsXILINX INC·Filed 2018·Granted Jul 28, 2020·3 cites·20 claims
- 2175US10644725B1Interleaved data block processing in low-density parity-check (LDPC) encoder and decoderXILINX INC·Filed 2018·Granted May 5, 2020·3 cites·20 claims
- 2271US11721373B2Shared multi-port memory from single portXILINX INC·Filed 2022·Granted Aug 8, 2023·0 cites·18 claims
- 2369US10484021B1Log-likelihood ratio processing for linear block code decodingXILINX INC·Filed 2018·Granted Nov 19, 2019·2 cites·13 claims
- 2440US8365109B1Determining efficient buffering for multi-dimensional datastream applicationsXILINX INC·Filed 2012·Granted Jan 29, 2013·0 cites·17 claims
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →