Inventor
PUDIPEDDI BHARADWAJ
US19 patents
⚠️ This page may combine multiple inventors who share the name “PUDIPEDDI BHARADWAJ”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
MICROSOFT TECHNOLOGY LICENSING LLC
11 patentsUS11436491B2Sep 6, 2022
System and method for improving convolutional neural network-based machine learning models
MICROSOFT TECHNOLOGY LICENSING LLC2 citations71
US11354579B2Jun 7, 2022
Dynamic multi-layer execution for artificial intelligence modeling
MICROSOFT TECHNOLOGY LICENSING LLC4 citations71
US11675654B2Jun 13, 2023
Systems and methods for error recovery
MICROSOFT TECHNOLOGY LICENSING LLC3 citations70
US11436019B2Sep 6, 2022
Data parallelism in distributed training of artificial intelligence models
MICROSOFT TECHNOLOGY LICENSING LLC5 citations68
US11520592B2Dec 6, 2022
Executing large artificial intelligence models on memory-constrained devices
MICROSOFT TECHNOLOGY LICENSING LLC2 citations67
US12353984B2Jul 8, 2025
Hardware-assisted gradient optimization using streamed gradients
MICROSOFT TECHNOLOGY LICENSING LLC0 citations62
US11681905B2Jun 20, 2023
Hardware-assisted gradient optimization using streamed gradients
MICROSOFT TECHNOLOGY LICENSING LLC0 citations62
US11615301B2Mar 28, 2023
Lossless exponent and lossy mantissa weight compression for training deep neural networks
MICROSOFT TECHNOLOGY LICENSING LLC1 citations62
US11226859B2Jan 18, 2022
Systems and methods for error recovery
MICROSOFT TECHNOLOGY LICENSING LLC0 citations60
US11651228B2May 16, 2023
Dual-momentum gradient optimization with reduced memory requirements
MICROSOFT TECHNOLOGY LICENSING LLC0 citations51
US12505340B2Dec 23, 2025
Stash balancing in model parallelism
MICROSOFT TECHNOLOGY LICENSING LLC0 citations41
INTEL CORP
5 patentsUS7765352B2Jul 27, 2010
Reducing core wake-up latency in a computer system
INTEL CORP6 citations73
US7603504B2Oct 13, 2009
Reducing core wake-up latency in a computer system
INTEL CORP1 citations51
US7447877B2Nov 4, 2008
Method and apparatus for converting memory instructions to prefetch operations during a thread switch window
INTEL CORP0 citations50
US7779210B2Aug 17, 2010
Avoiding snoop response dependency
INTEL CORP0 citations48
US7813288B2Oct 12, 2010
Transaction detection in link based computing system
INTEL CORP0 citations40