Inventor

VAHIDSAFA ALI

US34 patents

⚠️ This page may combine multiple inventors who share the name “VAHIDSAFA ALI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

VAHIDSAFA ALI

ORACLE INT CORP

Testing of SRAMS

High speed functional test vectors in low power test conditions of a digital integrated circuit

Drift compensation for a real time clock circuit

Rotational synchronizer circuit for metastablity resolution

Method for migrating CPU state from an inoperable core to a spare core

Method for migrating CPU state from an inoperable core to a spare core

Method for migrating CPU state from an inoperable core to a spare core

Simultaneous transition testing of different clock domains in a digital integrated circuit

Method for migrating CPU state from an inoperable core to a spare core

Method for migrating CPU state from an inoperable core to a spare core

Fault-tolerant cache coherence over a lossy network

Systems and methods for retiring and unretiring cache lines

Managing failed memory modules

Memory migration in presence of live memory traffic

Method and system for removal of a cache agent

Unified tool for automatic design constraints generation and verification

Combo dynamic flop with scan

Distributed mechanism for clock and reset control in a microprocessor

Mixing of low speed and high speed clocks to improve test precision of a digital integrated circuit

Method and apparatus for synchronizing the time reference of a dynamically activated processor to the system time reference

Inter-processor bus link and switch chip failure recovery

Cycle deterministic functional testing of a chip with asynchronous clock domains

Fault-tolerant cache coherence over a lossy network

Narrow-parallel scan-based device testing

VAHIDSAFA ALI

Method and apparatus for distributed generation of multiple configurable ratioed clock domains within a high speed domain

Hybrid hardwired/programmable reset sequence controller

SRAM macro test flop

Mechanism for consistent core hang detection in a a processor core

AMDAHL CORP

Method and apparatus for arbitration and serialization in a multiprocessor system

FEEHRER JOHN R

Interrupt processing unit for preventing interrupt loss

HWANG CHANGKU

Wide-range glitch-free asynchronous clock switch

SIVARAMAKRISHNAN RAMASWAMY

Systems and methods for retiring and unretiring cache lines

MASLEID ROBERT P

Combo static flop with full test

TURULLOLS SEBASTIAN

Constant frequency architectural timer in a dynamic clock domain