Inventor
BURNS JAMES S
US31 patents
⚠️ This page may combine multiple inventors who share the name “BURNS JAMES S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
16 patentsUS7111178B2Sep 19, 2006
Method and apparatus for adjusting the voltage and frequency to minimize power dissipation in a multiprocessor system
INTEL CORP111 citations98
US6931559B2Aug 16, 2005
Multiple mode power throttle mechanism
INTEL CORP67 citations97
US6898694B2May 24, 2005
High instruction fetch bandwidth in multithread processor using temporary instruction cache to deliver portion of cache line in subsequent clock cycle
INTEL CORP59 citations96
US7464276B2Dec 9, 2008
Method and apparatus for adjusting the voltage and frequency to minimize power dissipation in a multiprocessor system in response to compute load
INTEL CORP38 citations92
US7281140B2Oct 9, 2007
Digital throttle for multiple operating points
INTEL CORP31 citations92
US7062933B2Jun 20, 2006
Separate thermal and electrical throttling limits in processors
INTEL CORP37 citations92
US9502082B1Nov 22, 2016
Power management in dual memory platforms
INTEL CORP12 citations79
US7765352B2Jul 27, 2010
Reducing core wake-up latency in a computer system
INTEL CORP6 citations73
US9568978B2Feb 14, 2017
Controlling power consumption in processor-based systems and components thereof
INTEL CORP3 citations72
US9335813B2May 10, 2016
Method and system for run-time reallocation of leakage current and dynamic power supply current
INTEL CORP5 citations72
US8904205B2Dec 2, 2014
Increasing power efficiency of turbo mode operation in a processor
INTEL CORP4 citations71
US8683240B2Mar 25, 2014
Increasing power efficiency of turbo mode operation in a processor
INTEL CORP4 citations71
US7124309B2Oct 17, 2006
Method, system, and apparatus for an efficient power dissipation
INTEL CORP7 citations66
US9557804B2Jan 31, 2017
Dynamic power limit sharing in a platform
INTEL CORP1 citations51
US7603504B2Oct 13, 2009
Reducing core wake-up latency in a computer system
INTEL CORP1 citations51
US7685451B2Mar 23, 2010
Method and apparatus to limit current-change induced voltage changes in a microcircuit
INTEL CORP1 citations49
UNIV MICHIGAN REGENTS
5 patentsUS10249389B2Apr 2, 2019
Individual and cohort pharmacological phenotype prediction platform
UNIV MICHIGAN REGENTS32 citations91
US10553318B2Feb 4, 2020
Individual and cohort pharmacological phenotype prediction platform
UNIV MICHIGAN REGENTS6 citations81
US11984208B2May 14, 2024
Methods and system for the reconstruction of drug response and disease networks and uses thereof
UNIV MICHIGAN REGENTS2 citations70
US10867702B2Dec 15, 2020
Individual and cohort pharmacological phenotype prediction platform
UNIV MICHIGAN REGENTS3 citations70
US12211601B2Jan 28, 2025
Methods and system for the reconstruction of drug response and disease networks and uses thereof
UNIV MICHIGAN REGENTS1 citations61