Inventor

BERMAN AMIT

IL69 patents

⚠️ This page may combine multiple inventors who share the name “BERMAN AMIT”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BERMAN AMIT

SAMSUNG ELECTRONICS CO LTD

Hierarchical error correction code decoding using multistage concatenated codes

Hierarchical error correction code

Error detection and correction using machine learning

Hard decision decoding of non-volatile memory using machine learning

Low gate-count generalized concatenated code (GCC) by online calculation of syndromes instead of buffer

Super-HPC error correction code

Memory systems having reduced memory channel traffic and methods for operating the same

Energy efficient phase change random access memory cell array write via controller-side aggregation management

High-density storage system

Low-power data transfer from buffer to flash memory

Method of operating memory device using a compressed party difference, memory device using the same and memory system including the device

De-noising using multiple threshold-expert machine learning models

Method and apparatus for encoding and decoding data in memory system

Performing noise cancellation on a memory device using a neural network

Efficient hard decision decoding of generalized Reed-Solomon codes in presence of erasures and errors within the singleton bound

Machine-learning error-correcting code controller

Generalized hierarchical concatenated codes with fixed dimension and code length

Adaptive generalized concatenated codes for low power ECC with varying overhead

Dynamic online code-rate allocation according to wordline noise for adapative ECC in SSD/UFS

Two-dimensional generalized concatenated codes with sub-fields

ECC buffer reduction in a memory device

Automatic program voltage selection network

BCH fast soft decoding beyond the (d-1)/2 bound

ECC buffer reduction in a memory device

Automatic program voltage selection network

Memory cell level assignment using optimal level permutations in a non-volatile memory

Mobile data storage

Memory with adaptive slow-cell data compression

Low power ECC for eUFS

Denoising of intrinsic sneak current by cell location in PRAM

Generalized concatenated error correction coding scheme with locality

Fast polynomial division by monomial for Reed-Solomon ELP maintenance

Encoding and decoding of data using generalized LDPC codes

Encoding and decoding of data using generalized LDPC codes

Low-power systematic ECC encoder with balancing bits

Polar neural network decoder for memory devices

Setting optimal threshold voltages for reading data from a memory device based on a channel distribution

De-noising using multiple threshold-expert machine learning models

Threshold estimation in NAND flash devices

Nonvolatile memory bad row management

Acceleration of S-polar ECC throughput by scheduler

Acceleration of S-polar ECC throughput by scheduler

Reviving faulty NAND by AI data modulation

Meta model extension for a machine learning equalizer

Programming by self adjusting program voltage targets compensating for cell-to-cell interference and PE cycles

Computational storage acceleration using DRAM sharing between SSD in all-flash array

Soft reed-solomon decoder for a non-volatile memory

TECHNION RES & DEVELOPMENT FOUND LTD

Retired page utilization (RPU) for improved write capacity of solid state drives

TECHNION RES & DEV FOUNDATION

Minimal maximum-level programming

BIRK YITZHAK

Mitigating inter-cell coupling effects in non volatile memory (NVM) cells