Inventor

MITTAL SAMIR

US39 patents

⚠️ This page may combine multiple inventors who share the name “MITTAL SAMIR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MITTAL SAMIR

MICRON TECHNOLOGY INC

Predictive data orchestration in multi-tier memory systems

Predictive data orchestration in multi-tier memory systems

Predictive data orchestration in multi-tier memory systems

Remote direct memory access in multi-tier memory systems

Predictive paging to accelerate memory access

Remote direct memory access in multi-tier memory systems

Predictive paging to accelerate memory access

Memory sub-system including an in package sequencer separate from a controller

Memory sub-system including an in-package sequencer to perform error correction and memory testing operations

Memory access communications through message passing interface implemented in memory systems

NVMe direct virtualization with configurable storage

CPU cache flushing to persistent memory

Cross point array memory in a non-volatile dual in-line memory module

Scheduling of read operations and write operations based on a data bus mode

Scheduling of read operations and write operations based on a data bus mode

Memory systems having controllers embedded in packages of integrated circuit memory

CPU cache flushing to persistent memory

Memory sub-system including an in-package sequencer to perform error correction and memory testing operations

Memory sub-system including an in package sequencer separate from a controller

Memory tiering using PCIe connected far memory

Storing data based on a probability of a data graph

Providing bandwidth expansion for a memory sub-system including a sequencer separate from a controller

Memory access communications through message passing interface implemented in memory systems

Cache operations in a hybrid dual in-line memory module

Cross point array memory in a non-volatile dual in-line memory module

Memory tiering using PCIe connected far memory

Cache operations in a hybrid dual in-line memory module

Storing data based on a probability of a data graph

NVMe direct virtualization with configurable storage

Providing bandwidth expansion for a memory sub-system including a sequencer separate from a controller

Memory device data security based on content-addressable memory architecture

Memory device data security based on content-addressable memory architecture

Scheduling of read operations and write operations based on a data bus mode

SEAGATE TECHNOLOGY LLC

Method and apparatus for maintaining servo stability during actuator saturation

Interleaved repeatable runout estimation

Automatic model regulation in a disc drive servo system using model reference inverse

Zone based repeated runout error compensation

MITTAL SAMIR

Content distribution and aggregation

MATHUR PRIYADARSHEE DEEPTARAG

Secure content distribution