Inventor

PENG JIANWEI

CN40 patents

⚠️ This page may combine multiple inventors who share the name “PENG JIANWEI”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PENG JIANWEI

GLOBALFOUNDRIES INC

Method of forming vertical field effect transistors with different gate lengths and a resulting structure

Multi-phase source/drain/gate spacer-epi formation

Multi-layer spacer used in finFET

Metal-insulator-metal capacitors with enlarged contact areas

Multiple Fin heights with dielectric isolation

Multiple-layer spacers for field-effect transistors

Methods of forming EPI semiconductor material on the source/drain regions of a FinFET device

Single diffusion breaks formed with liner protection for source and drain regions

FinFET conformal junction and high EPI surface dopant concentration method and device

Multiple gate length device with self-aligned top junction

Method of forming a vertical field effect transistor (VFET) and a VFET structure

Boundary spacer structure and integration

Vertical-transport field-effect transistors with an etched-through source/drain cavity

Dual-curvature cavity for epitaxial semiconductor growth

Device with large EPI in FinFETs and method of manufacturing

Spacer integration scheme for FNET and PFET devices

Diffused contact extension dopants in a transistor device

Multiple-layer spacers for field-effect transistors

Methods of forming epi semiconductor material on a thinned fin in the source/drain regions of a FinFET device

FinFET conformal junction and high epi surface dopant concentration method and device

FinFET conformal junction and abrupt junction with reduced damage method and device

FinFET conformal junction and abrupt junction with reduced damage method and device

Self-aligned junction structures

Fabricating raised fins using ancillary fin structures

GLOBALFOUNDRIES US INC

Carbon implantation for thicker gate silicide

Semiconductor structure with shared well

Transistor arrays with controllable gate voltage

Substrates of semiconductor devices having varying thicknesses of semiconductor layers

Transistors with multiple silicide layers

Bipolar transistor with self-aligned asymmetric spacer

Semiconductor-on-insulator field effect transistor with performance-enhancing source/drain shapes and/or materials

Field-effect transistors with diffusion blocking spacer sections

Semiconductor device with different sized epitaxial structures

HANGZHOU PENNO PACKTECH CO LTD

Supporting plate

Equal-fork pallet

Method for processing a molded tray based on bamboo shavings

Method for processing a molded tray based on bamboo-wood mixed shavings

IBM

Backside diffusion break

CHINA TIESIJU CIVIL ENG GROUP

Highly thixotropic 3D printing concrete and manufacturing method therefor

ANHUI ZHONGTIE ENGINEERING MATERIAL TECH CO LTD

Modified dolomite powder, preparation method thereof and concrete