Inventor

CHEN HAI-CHING

TW188 patents

⚠️ This page may combine multiple inventors who share the name “CHEN HAI-CHING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHEN HAI-CHING

TAIWAN SEMICONDUCTOR MFG CO LTD

Method and apparatus for forming self-aligned via with selectively deposited etching stop layer

Lithography using high selectivity spacers for pitch reduction

Ferroelectric field effect transistor devices and methods for forming the same

Selective deposition of barrier layer

Interconnect structure and method for forming the same

Semiconductor device comprising etch stop layer over dielectric layer and method of manufacture

Structure and method for interconnection with self-alignment

Semiconductor device and manufacturing method thereof

Lithography using high selectivity spacers for pitch reduction

Semiconductor device having a porous low-k structure

Porogen bonded gap filling material in semiconductor manufacturing

Method and apparatus for forming self-aligned via with selectively deposited etching stop layer

Self-aligned interconnection structure and method

Etchant and etching process

Method of forming semiconductor device comprising conductive feature, dielectric layer adjacent conductive feature, and etch stop layer on top surface of dielectric layer

Semiconductor device comprising cap layer over dielectric layer and method of manufacture

Dielectric capping structure overlying a conductive structure to increase stability

Metal layers for increasing polarization of ferroelectric memory device

Cocktail layer over gate dielectric layer of FET FeRAM

Dielectric capping structure overlying a conductive structure to increase stability

Stacked ferroelectric structure

Capping layer overlying dielectric structure to increase reliability

Interconnect strucutre with protective etch-stop

Dielectric capping structure overlying a conductive structure to increase stability

Graphene-assisted low-resistance interconnect structures and methods of formation thereof

Metal capping layer and methods thereof

Schemes for forming barrier layers for copper in interconnect structures

Methods for fabricating a low-resistance interconnect

Selective deposition method for forming semiconductor structure

Method and apparatus for forming self-aligned via with selectively deposited etching stop layer

Method and structure for semiconductor device having gate spacer protection layer

Package structure and methods of forming same

Method of fabrication polymer waveguide

Etchant and etching process for substrate of a semiconductor device

TAIWAN SEMICONDUCTOR MFG

System and method for dark field inspection

Lithography using high selectivity spacers for pitch reduction

Package structure and methods of forming same

Schemes for forming barrier layers for copper in interconnect structures

Package structure and methods of forming same

Interconnect structure and method of forming the same

Schemes for forming barrier layers for copper in interconnect structures

Light coupling device and methods of forming same

Schemes for forming barrier layers for copper in interconnect structures

Air gap for interconnect application

Integrated circuit devices with multi-dimensional pad structures

YU CHEN-HUA

Schemes for forming barrier layers for copper in interconnect structures

Interconnect structures

Schemes for forming barrier layers for copper in interconnect structures

TSENG CHUN-HAO

Method of fabricating a polymer waveguide

LO CHING-YU

Liner formation in 3DIC structures