Inventor
TAUR YUAN
US15 patents
Patents
15 patentsUS6365465B1Apr 2, 2002
Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques
IBM169 citations99
US5767549AJun 16, 1998
SOI CMOS structure
IBM417 citations99
US6268640B1Jul 31, 2001
Forming steep lateral doping distribution at source/drain junctions
IBM171 citations98
US5780327AJul 14, 1998
Vertical double-gate field effect transistor
IBM68 citations96
US5689127ANov 18, 1997
Vertical double-gate field effect transistor
IBM71 citations96
US5646058AJul 8, 1997
Method for fabricating a self-aligned double-gate MOSFET by selective lateral epitaxy
IBM93 citations96
US5604368AFeb 18, 1997
Self-aligned double-gate MOSFET by selective lateral epitaxy
IBM52 citations96
US4585342AApr 29, 1986
System for real-time monitoring the characteristics, variations and alignment errors of lithography structures
IBM95 citations96
US5541427AJul 30, 1996
SRAM cell with capacitor
IBM87 citations95
US6759710B2Jul 6, 2004
Self-aligned double-gate MOSFET by selective epitaxy and silicon wafer bonding techniques
IBM28 citations92
US6143635ANov 7, 2000
Field effect transistors with improved implants and method for making such transistors
IBM37 citations92
US6040214AMar 21, 2000
Method for making field effect transistors having sub-lithographic gates with vertical side walls
IBM47 citations92
US5298786AMar 29, 1994
SOI lateral bipolar transistor with edge-strapped base contact and method of fabricating same
IBM43 citations92
US4509991AApr 9, 1985
Single mask process for fabricating CMOS structure
IBM21 citations82
US6593617B1Jul 15, 2003
Field effect transistors with vertical gate side walls and method for making such transistors
IBM5 citations62