Inventor

SAVIGNAC DOMINIQUE

DE52 patents

⚠️ This page may combine multiple inventors who share the name “SAVIGNAC DOMINIQUE”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SAVIGNAC DOMINIQUE

INFINEON TECHNOLOGIES AG

Semiconductor memory array with serial control/address bus

Memory configuration with a central connection area

Integrated circuit chip and integrated device

Data memory system and method for transferring data into a data memory

Memory module with a clock signal regeneration circuit and a register circuit for temporarily storing the incoming command and address signals

Method for fabricating an integrated circuit, in particular an antifuse

Semiconductor memory configuration with dummy components on continuous diffusion regions

Test circuit for testing a digital semiconductor circuit configuration

Memory device, memory controller and memory system having bidirectional clock lines

Semiconductor memory system and method for the transfer of write and read data signals in a semiconductor memory system

Semiconductor memory configuration with a bit-line twist

Semiconductor memory device including a signal control device and method of operating the same

Memory system with two clock lines and a memory device

Integrated semiconductor circuit having transistors that are switched with different frequencies

Volatile semiconductor memory and mobile device

Dicing configuration for separating a semiconductor component from a semiconductor wafer

Integrated memory with a buffer circuit

Buffer circuit

Method and apparatus for optimizing the functioning of DRAM memory elements

Semiconductor module for burn-in test configuration

Method for producing circuit structures on a semiconductor substrate and semiconductor configuration with functional circuit structures and dummy circuit structures

Integrated memory having memory cells and buffer capacitors

Method for reading and storing binary memory cells signals and circuit arrangement

SIEMENS AG

Charge pump

Conductor track configuration for very large-scale integrated circuits

Integrated circuit for generating a reset signal

CMOS input stage

Method for data transfer for a semiconductor memory using combined control signals to provide high speed transfer, and semiconductor memory for carrying out the method

Column redundance circuit configuration for a memory

Method for non-destructive identification for electronic inhomogeneities in semiconductor layers

Integrated semiconductor memory with parallel test capability and redundancy method

Fuse refresh circuit

Integrated semiconductor chip with modular dummy structures

Integrated semiconductor circuit having dummy structures

Configuration for identifying contact faults during the testing of integrated circuits

Redundant circuit configuration for an integrated semiconductor memory

Voltage generator circuit

Regulating circuit for a substrate bias voltage generator

Circuit apparatus for evaluating the data content of memory cells

Fuse bank

Integrated circuit with ESD protection

Circuit array for amplifying and holding data with different supply

QIMONDA AG

Integrated circuit, chip stack and data processing system

Memory dies for flexible use and method for configuring memory dies

Semiconductor memory device and method with a changeable substrate potential

Integrated circuit and method of operating such a circuit

Integrated circuit with buried control line structures

RUCKERBAUER HERMANN

Chip, multi-chip system in a method for performing a refresh of a memory array

NIRSCHL THOMAS

Memory and method for programming memory cells

ROLFF HAIKO

Lithographic mask and method of forming a lithographic mask