Inventor

SHAEFFER IAN

US141 patents

⚠️ This page may combine multiple inventors who share the name “SHAEFFER IAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SHAEFFER IAN

RAMBUS INC

Memory system topologies including a buffer device and an integrated circuit memory device

Memory system topologies including a buffer device and an integrated circuit memory device

Memory device comprising programmable command-and-address and/or data interfaces

Memory error detection

Memory error detection

Method and apparatus for calibrating write timing in a memory system

Memory error detection

On-die termination of address and command signals

On-die termination

On-die termination

Memory with alternative command interfaces

Memory error detection

Memory error detection

System including a buffered memory module

Memory system topologies including a buffer device and an integrated circuit memory device

Folded memory modules

System to detect and identify errors in control information, read data and/or write data

Memory access during memory calibration

Memory device comprising programmable command-and-address and/or data interfaces

Memory component with command-triggered data clock distribution

Memory system topologies including a memory die stack

Folded memory modules

Memory access during memory calibration

Memory device comprising programmable command-and-address and/or data interfaces

Memory system topologies including a buffer device and an integrated circuit memory device

Memory error detection

Memory system topologies including a buffer device and an integrated circuit memory device

On-die termination

Method and apparatus for calibrating write timing in a memory system

Memory access during memory calibration

Memory device comprising programmable command-and-address and/or data interfaces

On-die termination

Memory system topologies including a buffer device and an integrated circuit memory device

Memory components and controllers that calibrate multiphase synchronous timing references

Memory device comprising programmable command-and-address and/or data interfaces

Memory repair using external tags

Memory component with staggered power-down exit

Memory access during memory calibration

Method and apparatus for calibrating write timing in a memory system

SHAEFFER IAN

Memory system topologies including a buffer device and an integrated circuit memory device

Memory signal buffers and modules supporting variable access granularity

Memory access during memory calibration

Memory buffers and modules supporting dynamic point-to-point connections

On-die termination

Power-management for integrated circuits

Protocol including a command-specified timing reference signal

Time multiplexing at different rates to access different memory types

GIOVANNINI THOMAS J

Method and apparatus for calibrating write timing in a memory system

Method and apparatus for calibrating write timing in a memory system

BEST SCOTT C

Coordinating memory operations using memory-device generated reference signals