Inventor
HEGDE SURYANARAYAN G
US19 patents
Patents
19 patentsUS5392177AFeb 21, 1995
Sealed DASD having humidity control and method of making same
IBM58 citations96
US4931887AJun 5, 1990
Capacitive measurement and control of the fly height of a recording slider
IBM92 citations96
US7453123B2Nov 18, 2008
Self-aligned planar double-gate transistor structure
IBM15 citations92
US7205185B2Apr 17, 2007
Self-aligned planar double-gate process by self-aligned oxidation
IBM26 citations92
US6878978B2Apr 12, 2005
CMOS performance enhancement using localized voids and extended defects
IBM15 citations92
US6833569B2Dec 21, 2004
Self-aligned planar double-gate process by amorphization
IBM24 citations92
US6329704B1Dec 11, 2001
Ultra-shallow junction dopant layer having a peak concentration within a dielectric layer
IBM34 citations92
US6297086B1Oct 2, 2001
Application of excimer laser anneal to DRAM processing
IBM21 citations92
US6150670ANov 21, 2000
Process for fabricating a uniform gate oxide of a vertical transistor
IBM22 citations92
US5977787ANov 2, 1999
Large area multiple-chip probe assembly and method of making the same
IBM82 citations91
US5115664AMay 26, 1992
Tunable feedback transducer for transient friction measurement
IBM23 citations90
US5875171AFeb 23, 1999
Interlocking disk stack that prevents disk slip in a storage disk
IBM33 citations89
US6803270B2Oct 12, 2004
CMOS performance enhancement using localized voids and extended defects
IBM18 citations88
US6569781B1May 27, 2003
Method of forming an ultra-thin oxide layer on a silicon substrate by implantation of nitrogen through a sacrificial layer and subsequent annealing prior to oxide formation
IBM17 citations84
US6387782B2May 14, 2002
Process of forming an ultra-shallow junction dopant layer having a peak concentration within a dielectric layer
IBM6 citations74
US6727142B1Apr 27, 2004
Orientation independent oxidation of nitrided silicon
IBM8 citations73
US6348388B1Feb 19, 2002
Process for fabricating a uniform gate oxide of a vertical transistor
IBM12 citations73
US6514843B2Feb 4, 2003
Method of enhanced oxidation of MOS transistor gate corners
IBM10 citations70
US6858488B2Feb 22, 2005
CMOS performance enhancement using localized voids and extended defects
IBM2 citations63