Inventor

GOEL SANDEEP KUMAR

US106 patents

⚠️ This page may combine multiple inventors who share the name “GOEL SANDEEP KUMAR”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

GOEL SANDEEP KUMAR

TAIWAN SEMICONDUCTOR MFG CO LTD

Integrated circuit design method, system and computer program product

Method and system for reducing migration errors

Integrated circuit design method, system and computer program product

Method and system for reducing migration errors

System and method for ESL modeling of machine learning

Circuit and method for diagnosing scan chain failures

Bidirectional scan chain structure and method

Multi-dimensional integrated circuit structures and methods of forming the same

Circuit and method for monolithic stacked integrated circuit testing

Fault diagnostics

Phase-locked loop monitor circuit

Device with self-authentication

Function safety and fault management modeling at electrical system level (ESL)

Phase-locked loop monitor circuit

Scan architecture for interconnect testing in 3D integrated circuits

Phase-locked loop monitor circuit

System and method for validating stacked dies by comparing connections

Scan chains with multi-bit cells and methods for testing the same

Circuit and method for diagnosing scan chain failures

Probe card partition scheme

Circuit and method for diagnosing scan chain failures

Device with self-authentication

System and method for ESL modeling of machine learning

Scan architecture for interconnect testing in 3D integrated circuits

Network-on-chip system and a method of generating the same

Integrated circuit design method, system and computer program product

Method and system for reducing migration errors

System and method for ESL modeling of machine learning

Scan architecture for interconnect testing in 3D integrated circuits

Systems and methods to detect cell-internal defects

Device with self-authentication

GOEL SANDEEP KUMAR

System and method for testing stacked dies

DRAM repair architecture for wide I/O DRAM based 2.5D/3D system chips

Probe card partition scheme

Circuits and methods for testing through-silicon vias

Circuit and method for diagnosing scan chain failures

Interposers of 3-dimensional integrated circuit package systems and methods of designing the same

DRAM test architecture for wide I/O DRAM based 2.5D/3D system chips

TAIWAN SEMICONDUCTOR MFG

System and method for testing stacked dies

Reducing design verification time while maximizing system functional coverage

Circuit and method for monolithic stacked integrated circuit testing

Multi-dimensional integrated circuit structures and methods of forming the same

Circuit and method for monolithic stacked integrated circuit testing

Wafer on wafer stack method of forming and method of using the same

SEMMELMEYER MARK

Multi-dimensional integrated circuit structures and methods of forming the same

MEHTA ASHOK

Stacked die interconnect validation

KONINKL PHILIPS ELECTRONICS NV

Testing of circuit with plural clock domains

DEVTA-PRASANNA NARENDRA

System and device for reducing instantaneous voltage droop during a scan shift operation

MARINISSEN ERIK J

Testing of an integrated circuit that contains secret information

WANG MILL-JER

Test probing structure