Inventor

KAHNG ANDREW B

US32 patents

⚠️ This page may combine multiple inventors who share the name “KAHNG ANDREW B”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

KAHNG ANDREW B

TELA INNOVATIONS INC

Method and system for placing layout objects in a standard-cell layout

Method and system for topography-aware reticle enhancement

Method and system for finding an equivalent circuit representation for one or more elements in an integrated circuit

Standard cells having transistors annotated for gate-length biasing

System and method for varying the starting conditions for a resolution enhancement program to improve the probability that design goals will be met

System and method for performing transistor-level static performance analysis using cell-level static analysis tools

Arrangement of fill unit elements in an integrated circuit interconnect layer

Layout description having enhanced fill annotation

Method of designing a digital circuit by correlating different static timing analyzers

Gate-length biasing for digital circuit optimization

GUPTA PUNEET

Methods for gate-length biasing using annotation data

Standard cells having transistors annotated for gate-length biasing

Gate-length biasing for digital circuit optimization

Standard cells having transistors annotated for gate-length biasing

Standard cells having transistors annotated for gate-length biasing

Standard cells having transistors annotated for gate-length biasing

Standard cells having transistors annotated for gate-length biasing

UNIV CALIFORNIA

Method, apparatus and system for designing an integrated circuit including generating at least one auxiliary pattern for cell-based optical proximity correction

Layout decomposition for double patterning lithography

Floorplan evaluation, global routing, and buffer insertion for integrated circuits

Method and apparatus for detecting lithographic hotspots in a circuit layout

IC layout adjustment method and tool for improving dielectric reliability at interconnects

Multi-die IC layout methods with awareness of mix and match die integration

Diffusion-based method and apparatus for determining circuit interconnect voltage response

KAHNG ANDREW B

Layout decomposition for double patterning lithography

Tool for modifying mask design layout

Accuracy configurable adders and methods

UNIV MICHIGAN

Method for correcting a mask design layout

BLAZE DFM INC

Gate-length biasing for digital circuit optimization

UNIVERISITY OF CALIFORNIA

Method for correcting a mask design layout

COX JONATHAN

Internet telephony through hosts

PARK BONG IL

Data-retained power-gating circuit and devices including the same