Inventor

RANGACHARI SUNDARRAJAN

IN28 patents

⚠️ This page may combine multiple inventors who share the name “RANGACHARI SUNDARRAJAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

RANGACHARI SUNDARRAJAN

TEXAS INSTRUMENTS INC

Self test for safety logic

Systems and methods of low power decimation filter for sigma delta ADC

Dithered M by N clock dividers

Direct over-sampled pulse shaping circuit with flip flops and LUT

Low-complexity inverse sinc for RF sampling transmitters

Transformation based filter for interpolation or decimation

Transistion fault testing of funtionally asynchronous paths in an integrated circuit

Weather band receiver

Clock pulse generator

Self test for safety logic

Frequency-domain IQ mismatch estimation

Self test for safety logic

Digital clock generation with randomized division of a source clock

Low-complexity inverse sinc for RF sampling transmitters

Transition fault testing of functionally asynchronous paths in an integrated circuit

Low power digital modes for duty-cycled integrated transceivers

Transition fault test (TFT) clock receiver system

Transformation based filter for interpolation or decimation

Multiplier-based programmable filters

Systems and methods of variable fractional rate digital resampling

Dithered M by N clock dividers

Methods and systems for generation of balanced secondary clocks from root clock

Memory compression operable for non-contiguous write/read addresses

Memory compression operable for non-contiguous write/read addresses

Power efficient crest factor reduction

Digital downconverter with digital oscillator frequency error correction

Current reduction in digital circuits

PRATHAPAN INDU

Apparatus and method for reducing interference signals in an integrated circuit using multiphase clocks