Inventor

PARAT KRISHNA

US42 patents

⚠️ This page may combine multiple inventors who share the name “PARAT KRISHNA”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PARAT KRISHNA

INTEL CORP

Integrated memory cell and method of fabrication

Breakdown-tiggered transient discharge circuit

Method of fabrication of a novel flash integrated circuit

Dual trench isolation using single critical lithographic patterning

Integrated memory cell and method of fabrication

Dual trench isolation using single critical lithographic patterning

Memory arrays with bonded and shared logic circuitry

Method of forming non-volatile memory cell using sacrificial pillar spacers and non-volatile memory cell formed according to the method

Apparatuses, systems, and methods for heating a memory device

Flash memory components and methods

Memory device and method for erasing memory

Boosting seed voltage for a memory device

3-dimensional flash memory with increased floating gate length

Isolated P-well architecture for a memory device

Floating gate structures

Method and apparatus to mitigate hot electron read disturbs in 3D NAND devices

Modified floating gate and dielectric layer geometry in 3D memory arrays

Memory device with reduced capacitance

Channel conductivity in memory structures

Managing floating gate-to-floating gate spacing to support scalability

MICRON TECHNOLOGY INC

Memory device having improved programming operation

Memory devices and apparatus configured to apply positive voltage levels to data lines for memory cells selected for and inhibited from programming

Memory devices and programming memory arrays thereof

Sense flags in a memory device

Memory devices and apparatus configured to apply positive voltage levels to data lines for memory cells selected for and inhibited from programming

Sense flags in a memory device

Sense operation flags in a memory device

Memory devices that apply a programming potential to a memory cell in a string coupled to a source and data line concurrently with biasing the data line to a greater potential than the source

Operating memory devices to apply a programming potential to a memory cell in a string coupled to a source and data line concurrently with biasing the data line to a greater potential than the source

Sense operation flags in a memory device

GODA AKIRA

Independent well bias management in a memory device

Memory devices and methods of operating memory devices including applying a potential to a source and a select gate between the source and a string of memory cells while performing a program operation on a memory cell in the string

Memory devices and programming memory arrays thereof

Independent well bias management in a memory device

Intel NDTM US LLC

Method and apparatus to mitigate hot electron read disturbs in 3D nand devices

Weak erase pulse

3D NAND with inter-wordline airgap

Block-to-block isolation and deep contact using pillars in a memory array

INTEL CORPORAITON

Method and apparatus for providing electrostatic discharge protection for high voltage inputs

DAMLE PRASHANT S

Memory device having improved programming operation

AHMED SHAFQAT

Sense operation flags in a memory device

KALAVADE PRANAV

Apparatus and methods for improved flash cell characteristics