Inventor

BREWER TONY M

US165 patents

⚠️ This page may combine multiple inventors who share the name “BREWER TONY M”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BREWER TONY M

MICRON TECHNOLOGY INC

Backpressure control using a stop signal for a multi-threaded, self-scheduling reconfigurable computing fabric

Efficient loop execution for a multi-threaded, self-scheduling reconfigurable computing fabric

3D stacked integrated circuits having functional blocks configured to accelerate artificial neural network (ANN) computation

3D stacked integrated circuits having failure management

Multiple data channel memory module architecture

System having a hybrid threading processor, a hybrid threading fabric having configurable computing elements, and a hybrid interconnection network

Memory device protection

Write-back cache policy to limit data transfer time to a memory device

Mechanism to trigger early termination of cooperating processes

Debugging dataflow computer architectures

System having a hybrid threading processor, a hybrid threading fabric having configurable computing elements, and a hybrid interconnection network

3D stacked integrated circuits having functional blocks configured to accelerate artificial neural network (ANN) computation

Functional blocks implemented by 3D stacked integrated circuit

Power and temperature management for functional blocks implemented by a 3D stacked integrated circuit

3D stacked integrated circuits having functional blocks configured to provide redundancy sites

Multiple data channel memory module architecture

Multiple data channel memory module architecture

Undo capability for memory devices

Power and temperature management for functional blocks implemented by a 3D stacked integrated circuit

System having a hybrid threading processor, a hybrid threading fabric having configurable computing elements, and a hybrid interconnection network

Multi-threaded, self-scheduling processor

Thread commencement using a work descriptor packet in a self-scheduling processor

3D stacked integrated circuits having functional blocks configured to accelerate artificial neural network (ANN) computation

3D stacked integrated circuits having functional blocks configured to provide redundancy sites

Row clear features for memory devices and associated methods and systems

Loop execution control for a multi-threaded, self-scheduling reconfigurable computing fabric using a reenter queue

CHIARO NETWORKS LTD

System and method for router queue and congestion management

System and method for router central arbitration

Router line card protection using one-for-N redundancy

System and method for router packet control and ordering

Router switch fabric protection using forward error correction

System and method for router arbiter protection switching

Fast decision threshold controller for burst-mode receiver

HEWLETT PACKARD CO

Memory error correction using redundant sliced memory and standard ECC mechanisms

Optimizing data movement with hardware operations

Memory error containment in network cache environment via restricted access

Time of century counter synchronization using a SCI interconnect

Scalable resynchronization of remote counters

HEWLETT PACKARD DEVELOPMENT CO

Protocol for insuring exactly once semantics of transactions across an unordered, unreliable network

Virtual memory address translation control by TLB purge monitoring

Virtual memory translation control by TLB purge monitoring

BREWER TONY M

Memory interleave for heterogeneous computing

Multiple data channel memory module architecture

Memory interleave for heterogeneous computing

CONVEX COMPUTER CORP

Parallel processing computer system interconnections utilizing unidirectional communication links with separate request and response lines for direct communication or using a crossbar switching device

Scalable parallel processing systems wherein each hypernode has plural processing modules interconnected by crossbar and each processing module has SCI circuitry for forming multi-dimensional network with other hypernodes

FOUNDRY NETWORKS INC

System and method for router data aggregation and delivery

JEREMY BENJAMIN AS RECEIVER FO

Router network protection using multiple facility interfaces

DATA GENERAL CORP

Method of addressing a computer memory

LODESTAR LICENSING GROUP LLC

Row clear features for memory devices and associated methods and systems