Inventor

CRASKE SIMON JOHN

GB84 patents

⚠️ This page may combine multiple inventors who share the name “CRASKE SIMON JOHN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CRASKE SIMON JOHN

ADVANCED RISC MACH LTD

Interrupt controller

Secure mechanism to switch between different domains of operation in a data processor

Performance by reducing transaction request ordering requirements

Data processing apparatus and method for handling instructions to be executed by processing circuitry

Generation of a computer program to test for correct operation of a data processing apparatus

Deferred system error exception handling in a data processing apparatus

Secure mode state data access tracking

Handling memory access protection and address translation in a data processing apparatus

Program loop control

Virtualisation supporting guest operating systems using memory protection units to determine permission of a memory access operation for a physical address

Context sensitive barriers with an implicit access ordering constraint for a victim context

Apparatus and method for triggering action

Event monitoring in a multi-threaded data processing apparatus

Allocating a debug instruction set based on the current operating state in a multi-instruction-set data processing apparatus

Data processing apparatus and method for protecting secure data and program code from non-secure access when switching between secure and less secure domains

Instruction pre-decoding of multiple instruction sets

Data processing apparatus and method for reducing trace bandwidth

Handling access attributes for data accesses

Branch instruction

Mode switching in dependence upon a number of active threads

Error correcting bits

Power efficient interrupt detection

Forming an executable program from a list of program instructions

Scoring mechanism for automatically generated test programs

Apparatus and method for performing linear interpolation

Variable-length-instruction processing modes

Apparatus and method for executing instruction using range information associated with a pointer

Register-provided-opcode instruction

Exception interception

Instruction issue according to in-order or out-of-order execution modes

Apparatus and method for executing debug instructions

Apparatus and method for handling memory access requests

Asymmetric coherency protocol for first and second processing circuitry having different levels of fault protection or fault detection

Selectively suppressing time intensive instructions based on a control value

Comparator and memory region detection circuitry and methods

Handling access attributes for data accesses

Data processing apparatus and method for protecting secure data and program code from non-secure access when switching between secure and less secure domains

Conditional selection of data elements

CRASKE SIMON JOHN

Data processing apparatus and method having integer state preservation function and floating point state preservation function

Barrel shifter

Decoding instructions from multiple instructions sets

Exchanging physical to logical register mapping for obfuscation purpose when instruction of no operational impact is executed

Conditional selection of data elements

AXFORD SIMON

Hardware driven processor state storage prior to entering a low power

Multi-region default memory map

SEAL DAVID JAMES

Conditional compare instruction

GILDAY DAVID MICHAEL

Data processing apparatus and method for identifying debug events

HORLEY JOHN MICHAEL

Processing apparatus, trace unit and diagnostic apparatus

PENTON ANTONY JOHN

Apparatus and method for performing fused multiply add floating point operation

APICAL LTD

Controlling a display device