Inventor
MUHAMMAD MUJAHID
US49 patents
⚠️ This page may combine multiple inventors who share the name “MUHAMMAD MUJAHID”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
35 patentsUS9281379B1Mar 8, 2016
Gate-all-around fin device
IBM31 citations98
US9818542B2Nov 14, 2017
Gate-all-around fin device
IBM19 citations96
US9590108B2Mar 7, 2017
Gate-all-around fin device
IBM20 citations96
US9397163B2Jul 19, 2016
Gate-all-around fin device
IBM19 citations96
US10381483B2Aug 13, 2019
Gate-all-around fin device
IBM5 citations93
US10147822B2Dec 4, 2018
Gate-all-around fin device
IBM5 citations93
US10090400B2Oct 2, 2018
Gate-all-around fin device
IBM6 citations93
US9978874B2May 22, 2018
Gate-all-around fin device
IBM6 citations93
US9923096B2Mar 20, 2018
Gate-all-around fin device
IBM12 citations93
US9911852B2Mar 6, 2018
Gate-all-around fin device
IBM8 citations93
US7203045B2Apr 10, 2007
High voltage ESD power clamp
IBM30 citations92
US10658514B2May 19, 2020
Gate-all-around fin device
IBM2 citations84
US10573754B2Feb 25, 2020
Gate-all around fin device
IBM4 citations84
US10381484B2Aug 13, 2019
Gate-all-around fin device
IBM3 citations84
US10090301B2Oct 2, 2018
Gate-all-around fin device
IBM4 citations84
US9236374B2Jan 12, 2016
Fin contacted electrostatic discharge (ESD) devices with improved heat distribution
IBM8 citations84
US9041127B2May 26, 2015
FinFET device technology with LDMOS structures for high voltage operations
IBM19 citations84
US7138313B2Nov 21, 2006
Method for creating a self-aligned SOI diode by removing a polysilicon gate during processing
IBM13 citations84
US7098513B2Aug 29, 2006
Low trigger voltage, low leakage ESD NFET
IBM11 citations84
US8803276B2Aug 12, 2014
Electrostatic discharge (ESD) device and method of fabricating
IBM6 citations83
US11141902B2Oct 12, 2021
Gate-all-around fin device
IBM0 citations73
US11130270B2Sep 28, 2021
Gate-all-around fin device
IBM0 citations73
US10974433B2Apr 13, 2021
Gate-all-around fin device
IBM1 citations73
US10940627B2Mar 9, 2021
Gate-all-around fin device
IBM0 citations73
US10593805B2Mar 17, 2020
Gate-all-around fin device
IBM1 citations73
US10388793B2Aug 20, 2019
Gate-all-around fin device
IBM1 citations73
US8354722B2Jan 15, 2013
SCR/MOS clamp for ESD protection of integrated circuits
IBM6 citations73
US8350329B2Jan 8, 2013
Low trigger voltage electrostatic discharge NFET in triple well CMOS technology
IBM6 citations73
US10770594B2Sep 8, 2020
Gate-all-around fin device
IBM0 citations63
US7457086B2Nov 25, 2008
High voltage ESD power clamp
IBM3 citations63
US9349732B2May 24, 2016
High voltage lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) having a deep fully depleted drain drift region
IBM0 citations52
US9059278B2Jun 16, 2015
High voltage lateral double-diffused metal oxide semiconductor field effect transistor (LDMOSFET) having a deep fully depleted drain drift region
IBM0 citations52
US10283959B2May 7, 2019
ESD state-controlled semiconductor-controlled rectifier
IBM0 citations42
US8363367B2Jan 29, 2013
Electrical overstress protection circuit
IBM0 citations42
US7005686B1Feb 28, 2006
Mixed voltage tolerant electrostatic discharge protection silicon controlled rectifier with enhanced turn-on time
IBM0 citations39
CAMPI JR JOHN B
4 patentsUS8760827B2Jun 24, 2014
Robust ESD protection circuit, method and design structure for tolerant and failsafe designs
CAMPI JR JOHN B12 citations83
US8299533B2Oct 30, 2012
Vertical NPNP structure in a triple well CMOS process
CAMPI JR JOHN B8 citations83
US8513738B2Aug 20, 2013
ESD field-effect transistor and integrated diffusion resistor
CAMPI JR JOHN B5 citations72
US8634172B2Jan 21, 2014
Silicon controlled rectifier based electrostatic discharge protection circuit with integrated JFETs, method of operation and design structure
CAMPI JR JOHN B1 citations51