Inventor

CHUNG ERIC S

US47 patents

⚠️ This page may combine multiple inventors who share the name “CHUNG ERIC S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CHUNG ERIC S

MICROSOFT TECHNOLOGY LICENSING LLC

Hardware node having a matrix vector unit with block-floating point processing

Hardware node with matrix-vector multiply tiles for neural network processing

Locally restoring functionality at acceleration components

Reconfiguring an acceleration component among interconnected acceleration components

Implementing a multi-component service using plural hardware acceleration components

Independently networkable hardware accelerators for increased workflow optimization

Flow control and congestion management for acceleration components configured to accelerate a service

Flow for quantized neural networks

Restoring service acceleration

Neural network activation compression with outlier block floating-point

Residual quantization for neural networks

Protecting communications with hardware accelerators for increased workflow security

Dynamic power routing to hardware accelerators

Systems and methods for hardware acceleration of data masking using a field programmable gate array

Training neural network accelerators using mixed precision data formats

Adjusting activation compression for neural network training

Neural network processor based on application specific synthesis specialization parameters

Matrix vector multiplier with a vector register file comprising a multi-port memory

Systems and methods for accelerating the computation of the exponential function

Residual quantization for neural networks

Fusing operators for neural network hardware accelerators

Neural network processing with chained instructions

Neural network processing with chained instructions

Neural network processing with the neural network model pinned to on-chip memories of hardware nodes

Hardware node with position-dependent memories for neural network processing

Machine learning model processing based on perplexity

Systems and methods for hardware acceleration of data masking

Neural network activation compression with non-uniform mantissas

Neural network activation compression with non-uniform mantissas

Outlier quantization for training and inference

Neural network activation compression with non-uniform mantissas

Subsampling training data during artificial neural network training

Transmission of messages by acceleration components configured to accelerate a service

Hardware implemented load balancing

Adjusting precision and topology parameters for neural network training based on a performance metric

Dynamic power routing to hardware accelerators

Dithered quantization of parameters during training with a machine learning tool

Neural network activation compression with narrow block floating-point

Reducing operations for training neural networks

Flow control and congestion management for acceleration components configured to accelerate a service

Hardware implemented load balancing

Data-aware model pruning for neural networks

Hierarchical and shared exponent floating point data types

Quantization-aware neural architecture search

Differential bit width neural architecture search

Block floating point computations using reduced bit-width vectors

MICROSOFT TECH LICESNING LLC

Multi-function unit for programmable hardware nodes for neural network processing