Inventor
PLOTNIKOV MIKHAIL
RU47 patents
⚠️ This page may combine multiple inventors who share the name “PLOTNIKOV MIKHAIL”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
40 patentsUS10846087B2Nov 24, 2020
Systems, apparatuses, and methods for broadcast arithmetic operations
INTEL CORP20 citations94
US10191744B2Jan 29, 2019
Apparatuses, methods, and systems for element sorting of vectors
INTEL CORP14 citations85
US10452398B2Oct 22, 2019
Methods, apparatus, instructions and logic to provide permute controls with leading zero count functionality
INTEL CORP3 citations84
US9804850B2Oct 31, 2017
Methods, apparatus, instructions and logic to provide permute controls with leading zero count functionality
INTEL CORP4 citations84
US9619229B2Apr 11, 2017
Collapsing of multiple nested loops, methods and instructions
INTEL CORP6 citations84
US9372692B2Jun 21, 2016
Methods, apparatus, instructions, and logic to provide permute controls with leading zero count functionality
INTEL CORP6 citations84
US11436010B2Sep 6, 2022
Method and apparatus for vectorizing indirect update loops
INTEL CORP4 citations73
US11042377B2Jun 22, 2021
Collapsing of multiple nested loops, methods, and instructions
INTEL CORP1 citations73
US10545761B2Jan 28, 2020
Methods, apparatus, instructions and logic to provide permute controls with leading zero count functionality
INTEL CORP2 citations73
US10025591B2Jul 17, 2018
Instruction for element offset calculation in a multi-dimensional array
INTEL CORP2 citations73
US9946544B2Apr 17, 2018
Methods, apparatus, instructions and logic to provide permute controls with leading zero count functionality
INTEL CORP2 citations73
US9424039B2Aug 23, 2016
Instruction for implementing vector loops of iterations having an iteration dependent condition
INTEL CORP3 citations73
US9910670B2Mar 6, 2018
Instruction set for eliminating misaligned memory accesses during processing of an array having misaligned data rows
INTEL CORP3 citations72
US9400650B2Jul 26, 2016
Read and write masks update instruction for vectorization of recursive computations over interdependent data
INTEL CORP3 citations72
US11934830B2Mar 19, 2024
Method and apparatus for data-ready memory operations
INTEL CORP0 citations62
US11640298B2May 2, 2023
Collapsing of multiple nested loops, methods, and instructions
INTEL CORP0 citations62
US11360771B2Jun 14, 2022
Method and apparatus for data-ready memory operations
INTEL CORP0 citations62
US10929133B2Feb 23, 2021
Apparatuses, methods, and systems for element sorting of vectors
INTEL CORP1 citations62
US10908898B2Feb 2, 2021
Vector instruction for accumulating and compressing values based on input mask
INTEL CORP0 citations62
US10884750B2Jan 5, 2021
Strideshift instruction for transposing bits inside vector register
INTEL CORP0 citations62
US10884744B2Jan 5, 2021
System and method of loop vectorization by compressing indices and data elements from iterations based on a control mask
INTEL CORP0 citations62
US10191740B2Jan 29, 2019
Deinterleave strided data elements processors, methods, systems, and instructions
INTEL CORP1 citations62
US12299501B2May 13, 2025
Technologies for managing data wait barrier operations
INTEL CORP0 citations52
US11169809B2Nov 9, 2021
Method and apparatus for converting scatter control elements to gather control elements used to sort vector data elements
INTEL CORP0 citations52
US10877758B2Dec 29, 2020
Collapsing of multiple nested loops, methods, and instructions
INTEL CORP0 citations52
US10740100B2Aug 11, 2020
Deinterleave strided data elements processors, methods, systems, and instructions
INTEL CORP0 citations52
US10503505B2Dec 10, 2019
Read and write masks update instruction for vectorization of recursive computations over independent data
INTEL CORP0 citations52
US10282204B2May 7, 2019
Systems, apparatuses, and methods for strided load
INTEL CORP0 citations52
US10268479B2Apr 23, 2019
Systems, apparatuses, and methods for broadcast compare addition
INTEL CORP0 citations52
US10108418B2Oct 23, 2018
Collapsing of multiple nested loops, methods, and instructions
INTEL CORP0 citations52
US10037208B2Jul 31, 2018
Multi-element instruction with different read and write masks
INTEL CORP0 citations52
US9934031B2Apr 3, 2018
Read and write masks update instruction for vectorization of recursive computations over independent data
INTEL CORP0 citations52
US9921837B2Mar 20, 2018
Instruction for implementing iterations having an iteration dependent condition with a vector loop
INTEL CORP0 citations52
US10223119B2Mar 5, 2019
Processors, methods, systems, and instructions to store source elements to corresponding unmasked result elements with propagation to masked result elements
INTEL CORP0 citations42
US10223113B2Mar 5, 2019
Processors, methods, systems, and instructions to store consecutive source elements to unmasked result elements with propagation to masked result elements
INTEL CORP0 citations42
US10191743B2Jan 29, 2019
Versatile packed data comparison processors, methods, systems, and instructions
INTEL CORP0 citations42
US11853757B2Dec 26, 2023
Vectorization of loops based on vector masks and vector count distances
INTEL CORP0 citations41
US10838720B2Nov 17, 2020
Methods and processors having instructions to determine middle, lowest, or highest values of corresponding elements of three vectors
INTEL CORP0 citations41
US9378182B2Jun 28, 2016
Vector move instruction controlled by read and write masks
INTEL CORP0 citations41
US10776093B2Sep 15, 2020
Vectorize store instructions method and apparatus
INTEL CORP0 citations36
HUGHES CHRISTOPHER J
4 patentsUS10162637B2Dec 25, 2018
Methods, apparatus, instructions and logic to provide permute controls with leading zero count functionality
HUGHES CHRISTOPHER J2 citations73
US10162639B2Dec 25, 2018
Methods, apparatus, instructions and logic to provide permute controls with leading zero count functionality
HUGHES CHRISTOPHER J2 citations73
US9740493B2Aug 22, 2017
System and method of loop vectorization by compressing indexes and data elements from iterations based on a control mask
HUGHES CHRISTOPHER J2 citations73
US10162638B2Dec 25, 2018
Methods, apparatus, instructions and logic to provide permute controls with leading zero count functionality
HUGHES CHRISTOPHER J0 citations52
PLOTNIKOV MIKHAIL
3 patentsUS9507593B2Nov 29, 2016
Instruction for element offset calculation in a multi-dimensional array
PLOTNIKOV MIKHAIL4 citations71
US9122475B2Sep 1, 2015
Instruction for shifting bits left with pulling ones into less significant bits
PLOTNIKOV MIKHAIL5 citations71
US9489196B2Nov 8, 2016
Multi-element instruction with different read and write masks
PLOTNIKOV MIKHAIL1 citations48