Inventor
NARAIKIN ANDREY
RU27 patents
⚠️ This page may combine multiple inventors who share the name “NARAIKIN ANDREY”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
19 patentsUS10452398B2Oct 22, 2019
Methods, apparatus, instructions and logic to provide permute controls with leading zero count functionality
INTEL CORP3 citations84
US9804850B2Oct 31, 2017
Methods, apparatus, instructions and logic to provide permute controls with leading zero count functionality
INTEL CORP4 citations84
US9619229B2Apr 11, 2017
Collapsing of multiple nested loops, methods and instructions
INTEL CORP6 citations84
US9372692B2Jun 21, 2016
Methods, apparatus, instructions, and logic to provide permute controls with leading zero count functionality
INTEL CORP6 citations84
US11436010B2Sep 6, 2022
Method and apparatus for vectorizing indirect update loops
INTEL CORP4 citations73
US11042377B2Jun 22, 2021
Collapsing of multiple nested loops, methods, and instructions
INTEL CORP1 citations73
US10545761B2Jan 28, 2020
Methods, apparatus, instructions and logic to provide permute controls with leading zero count functionality
INTEL CORP2 citations73
US10025591B2Jul 17, 2018
Instruction for element offset calculation in a multi-dimensional array
INTEL CORP2 citations73
US9946544B2Apr 17, 2018
Methods, apparatus, instructions and logic to provide permute controls with leading zero count functionality
INTEL CORP2 citations73
US9400650B2Jul 26, 2016
Read and write masks update instruction for vectorization of recursive computations over interdependent data
INTEL CORP3 citations72
US11640298B2May 2, 2023
Collapsing of multiple nested loops, methods, and instructions
INTEL CORP0 citations62
US10884744B2Jan 5, 2021
System and method of loop vectorization by compressing indices and data elements from iterations based on a control mask
INTEL CORP0 citations62
US10877758B2Dec 29, 2020
Collapsing of multiple nested loops, methods, and instructions
INTEL CORP0 citations52
US10503505B2Dec 10, 2019
Read and write masks update instruction for vectorization of recursive computations over independent data
INTEL CORP0 citations52
US10108418B2Oct 23, 2018
Collapsing of multiple nested loops, methods, and instructions
INTEL CORP0 citations52
US10037208B2Jul 31, 2018
Multi-element instruction with different read and write masks
INTEL CORP0 citations52
US9934031B2Apr 3, 2018
Read and write masks update instruction for vectorization of recursive computations over independent data
INTEL CORP0 citations52
US9684510B2Jun 20, 2017
Systems, apparatuses, and methods for performing a shuffle and operation (Shuffle-Op)
INTEL CORP0 citations51
US9378182B2Jun 28, 2016
Vector move instruction controlled by read and write masks
INTEL CORP0 citations41
HUGHES CHRISTOPHER J
4 patentsUS10162637B2Dec 25, 2018
Methods, apparatus, instructions and logic to provide permute controls with leading zero count functionality
HUGHES CHRISTOPHER J2 citations73
US10162639B2Dec 25, 2018
Methods, apparatus, instructions and logic to provide permute controls with leading zero count functionality
HUGHES CHRISTOPHER J2 citations73
US9740493B2Aug 22, 2017
System and method of loop vectorization by compressing indexes and data elements from iterations based on a control mask
HUGHES CHRISTOPHER J2 citations73
US10162638B2Dec 25, 2018
Methods, apparatus, instructions and logic to provide permute controls with leading zero count functionality
HUGHES CHRISTOPHER J0 citations52