Inventor

SUESS ALEXANDER J

US32 patents

⚠️ This page may combine multiple inventors who share the name “SUESS ALEXANDER J”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SUESS ALEXANDER J

IBM

System and method for correlated process pessimism removal for static timing analysis

Method for handling coupling effects in static timing analysis

Leverage cycle stealing within optimization flows

Variable accuracy parameter modeling in statistical timing

Optimizing placement of circuit resources using a globally accessible placement memory

Optimizing placement of circuit resources using a globally accessible placement memory

Method for fast incremental calculation of an impact of coupled noise on timing

Selection of corners and/or margins using statistical static timing analysis of an integrated circuit

Method for generating a skew schedule for a clock distribution network containing gating elements

Leverage cycle stealing within optimization flows

Leverage cycle stealing within optimization flows

Selection of corners and/or margins using statistical static timing analysis of an integrated circuit

Integration of functional analysis and common path pessimism removal in static timing analysis

Optimizing placement of circuit resources using a globally accessible placement memory

Optimizing placement of circuit resources using a globally accessible placement memory

Integration of functional analysis and common path pessimism removal in static timing analysis

Memory element graph-based placement in integrated circuit design

Leverage cycle stealing within optimization flows

Process and apparatus for estimating circuit delay

Memory element graph-based placement in integrated circuit design

Boundary assertion-based power recovery in integrated circuit design

Selection of corners and/or margins using statistical static timing analysis of an integrated circuit

Optimizing placement of circuit resources using a globally accessible placement memory

Parallel multi-threaded common path pessimism removal in multiple paths

Variable accuracy parameter modeling in statistical timing

Cell placement in a circuit with shared inputs and outputs

Parallel incremental global routing

Method of improving timing critical cells for physical design in the presence of local placement congestion

Automated region based optimization of chip manufacture

Managing virtual boundaries to enable lock-free concurrent region optimization of an integrated circuit

MUSANTE FRANK J

Method for enabling multiple incompatible or costly timing environment for efficient timing closure

ANTONY GEORGE

Native threshold voltage switching